miller.sim.rpt

使用VHDL实现基带码中密勒码的编解码

; |miller_encoder|encodeout[0]~reg0 ; |miller_encoder|encodeout[0]~reg0 ; regout           ;
; |miller_encoder|process0~8        ; |miller_encoder|process0~8        ; out0             ;
; |miller_encoder|process0~9        ; |miller_encoder|process0~9        ; out0             ;
; |miller_encoder|process0~11       ; |miller_encoder|process0~11       ; out0             ;
; |miller_encoder|sav1              ; |miller_encoder|sav1              ; regout           ;
; |miller_encoder|encodeout[1]~reg0 ; |miller_encoder|encodeout[1]~reg0 ; regout           ;
; |miller_encoder|sav2~0            ; |miller_encoder|sav2~0            ; out              ;
; |miller_encoder|sav2~1            ; |miller_encoder|sav2~1            ; out              ;
; |miller_encoder|sav2~2            ; |miller_encoder|sav2~2            ; out              ;
; |miller_encoder|sav2~3            ; |miller_encoder|sav2~3            ; out              ;
; |miller_encoder|sav2~4            ; |miller_encoder|sav2~4            ; out              ;
; |miller_encoder|sav2~5            ; |miller_encoder|sav2~5            ; out              ;
; |miller_encoder|sav2~6            ; |miller_encoder|sav2~6            ; out              ;
; |miller_encoder|sav2~7            ; |miller_encoder|sav2~7            ; out              ;
; |miller_encoder|sav2~8            ; |miller_encoder|sav2~8            ; out              ;
; |miller_encoder|sav2~9            ; |miller_encoder|sav2~9            ; out              ;
; |miller_encoder|sav2~10           ; |miller_encoder|sav2~10           ; out              ;
; |miller_encoder|sav2~11           ; |miller_encoder|sav2~11           ; out              ;
; |miller_encoder|sav2~12           ; |miller_encoder|sav2~12           ; out              ;
; |miller_encoder|sav2~13           ; |miller_encoder|sav2~13           ; out              ;
; |miller_encoder|sav2~14           ; |miller_encoder|sav2~14           ; out              ;
; |miller_encoder|sav2~15           ; |miller_encoder|sav2~15           ; out              ;
; |miller_encoder|sav1~0            ; |miller_encoder|sav1~0            ; out              ;
; |miller_encoder|sav1~1            ; |miller_encoder|sav1~1            ; out              ;
; |miller_encoder|sav1~2            ; |miller_encoder|sav1~2            ; out              ;
; |miller_encoder|sav1~3            ; |miller_encoder|sav1~3            ; out              ;
; |miller_encoder|sav1~4            ; |miller_encoder|sav1~4            ; out              ;
; |miller_encoder|sav1~5            ; |miller_encoder|sav1~5            ; out              ;
; |miller_encoder|sav1~6            ; |miller_encoder|sav1~6            ; out              ;
; |miller_encoder|sav1~7            ; |miller_encoder|sav1~7            ; out              ;
; |miller_encoder|encodeout[1]~2    ; |miller_encoder|encodeout[1]~2    ; out              ;
; |miller_encoder|sav2[1]           ; |miller_encoder|sav2[1]           ; regout           ;
; |miller_encoder|sav2[0]           ; |miller_encoder|sav2[0]           ; regout           ;
; |miller_encoder|encodeout[1]~3    ; |miller_encoder|encodeout[1]~3    ; out              ;
; |miller_encoder|encodeout[0]~4    ; |miller_encoder|encodeout[0]~4    ; out0             ;
; |miller_encoder|encodeout[0]~5    ; |miller_encoder|encodeout[0]~5    ; out              ;
; |miller_encoder|encodeout[0]~6    ; |miller_encoder|encodeout[0]~6    ; out0             ;
; |miller_encoder|encodeout[0]~7    ; |miller_encoder|encodeout[0]~7    ; out              ;
; |miller_encoder|encodeout[0]~8    ; |miller_encoder|encodeout[0]~8    ; out0             ;
; |miller_encoder|encodeout[0]~9    ; |miller_encoder|encodeout[0]~9    ; out              ;
; |miller_encoder|encodeout[0]~10   ; |miller_encoder|encodeout[0]~10   ; out0             ;
; |miller_encoder|encodeout[0]~11   ; |miller_encoder|encodeout[0]~11   ; out              ;
; |miller_encoder|encodeout[0]~12   ; |miller_encoder|encodeout[0]~12   ; out0             ;
; |miller_encoder|encodeout[0]~13   ; |miller_encoder|encodeout[0]~13   ; out              ;
; |miller_encoder|encodeout[0]~14   ; |miller_encoder|encodeout[0]~14   ; out0             ;
; |miller_encoder|encodeout[0]~15   ; |miller_encoder|encodeout[0]~15   ; out              ;
; |miller_encoder|encodeout[1]~16   ; |miller_encoder|encodeout[1]~16   ; out              ;
; |miller_encoder|encodeout[1]~17   ; |miller_encoder|encodeout[1]~17   ; out              ;
; |miller_encoder|encodeout[1]~18   ; |miller_encoder|encodeout[1]~18   ; out              ;
; |miller_encoder|encodeout[1]~19   ; |miller_encoder|encodeout[1]~19   ; out              ;
; |miller_encoder|encodeout[1]~20   ; |miller_encoder|encodeout[1]~20   ; out              ;
; |miller_encoder|datain            ; |miller_encoder|datain            ; out              ;
; |miller_encoder|clk               ; |miller_encoder|clk               ; out              ;
; |miller_encoder|encodeout[0]      ; |miller_encoder|encodeout[0]      ; pin_out          ;
; |miller_encoder|encodeout[1]      ; |miller_encoder|encodeout[1]      ; pin_out          ;
; |miller_encoder|Equal0~3          ; |miller_encoder|Equal0~3          ; out0             ;
; |miller_encoder|Equal1~3          ; |miller_encoder|Equal1~3          ; out0             ;
; |miller_encoder|Equal2~3          ; |miller_encoder|Equal2~3          ; out0             ;
; |miller_encoder|Equal3~3          ; |miller_encoder|Equal3~3          ; out0             ;
+-----------------------------------+-----------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                           ;
+--------------------------------+--------------------------------+------------------+
; Node Name                      ; Output Port Name               ; Output Port Type ;
+--------------------------------+--------------------------------+------------------+
; |miller_encoder|encodeout[0]~0 ; |miller_encoder|encodeout[0]~0 ; out              ;
; |miller_encoder|process0~10    ; |miller_encoder|process0~10    ; out0             ;
+--------------------------------+--------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                             ;
+---------------------------------+---------------------------------+------------------+
; Node Name                       ; Output Port Name                ; Output Port Type ;
+---------------------------------+---------------------------------+------------------+
; |miller_encoder|encodeout[0]~0  ; |miller_encoder|encodeout[0]~0  ; out              ;
; |miller_encoder|process0~10     ; |miller_encoder|process0~10     ; out0             ;
; |miller_encoder|encodeout[0]~en ; |miller_encoder|encodeout[0]~en ; regout           ;
; |miller_encoder|encodeout[1]~en ; |miller_encoder|encodeout[1]~en ; regout           ;
; |miller_encoder|en              ; |miller_encoder|en              ; out              ;
+---------------------------------+---------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Thu May 14 00:26:05 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off miller -c miller
Info: Using vector source file "E:/通信原理/实验五/miller/miller_encoder.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Warning: Found clock-sensitive change during active clock edge at time 120.0 ns on register "|miller_encoder|encodeout[0]~reg0"
Warning: Found clock-sensitive change during active clock edge at time 120.0 ns on register "|miller_encoder|sav1"
Warning: Found clock-sensitive change during active clock edge at time 120.0 ns on register "|miller_encoder|sav2[1]"
Warning: Found clock-sensitive change during active clock edge at time 120.0 ns on register "|miller_encoder|sav2[0]"
Warning: Found clock-sensitive change during active clock edge at time 160.0 ns on register "|miller_encoder|encodeout[1]~reg0"
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      93.15 %
Info: Number of transitions in simulation is 425
Info: Quartus II Simulator was successful. 0 errors, 5 warnings
    Info: Peak virtual memory: 106 megabytes
    Info: Processing ended: Thu May 14 00:26:06 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01