miller_decoder.vhd

来自「使用VHDL实现基带码中密勒码的编解码」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity miller_decoder is
port(encodein :in std_logic_vector(1 downto 0);
	 en   :in std_logic;
	 clk  :in std_logic;
	 decodeout:out std_logic
	 );
end ;

architecture func of miller_decoder is
begin
 process(en,clk,encodein)
  begin
   if(en='0') then
    decodeout<='Z';
   else
    if(clk 'event and clk='0') then
     if(encodein="11" or encodein="00") then
      decodeout<='0';
     elsif(encodein="10" or encodein="01") then
      decodeout<='1';
     end if;
    end if;
   end if;
 end process;
end func;