miller.map.rpt

使用VHDL实现基带码中密勒码的编解码

; Analysis & Synthesis Source Files Read                                                                              ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                 ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+
; miller_encoder.vhd               ; yes             ; User VHDL File  ; E:/通信原理/实验五/miller/miller_encoder.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Estimated Total logic elements              ; 6       ;
;                                             ;         ;
; Total combinational functions               ; 6       ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 5       ;
;     -- 3 input functions                    ; 1       ;
;     -- <=2 input functions                  ; 0       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 6       ;
;     -- arithmetic mode                      ; 0       ;
;                                             ;         ;
; Total registers                             ; 6       ;
;     -- Dedicated logic registers            ; 6       ;
;     -- I/O registers                        ; 0       ;
;                                             ;         ;
; I/O pins                                    ; 5       ;
; Maximum fan-out node                        ; sav2[1] ;
; Maximum fan-out                             ; 6       ;
; Total fan-out                               ; 45      ;
; Average fan-out                             ; 2.65    ;
+---------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |miller_encoder            ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 5    ; 0            ; |miller_encoder     ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------+
; Registers Removed During Synthesis                                  ;
+---------------------------------------+-----------------------------+
; Register name                         ; Reason for Removal          ;
+---------------------------------------+-----------------------------+
; encodeout[1]~en                       ; Merged with encodeout[0]~en ;
; Total Number of Removed Registers = 1 ;                             ;
+---------------------------------------+-----------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 6     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 1     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 6     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; sav1                                   ; 6       ;
; sav2[0]                                ; 6       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 16:1               ; 2 bits    ; 20 LEs        ; 6 LEs                ; 14 LEs                 ; Yes        ; |miller_encoder|encodeout[0]~reg0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Thu May 14 00:25:30 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off miller -c miller
Warning: Ignored assignments for entity "miller_encoder" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" is ignored
    Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" is ignored
    Warning: Assignment of entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -section_id Top is ignored
Info: Found 2 design units, including 1 entities, in source file miller_encoder.vhd
    Info: Found design unit 1: miller_encoder-func
    Info: Found entity 1: miller_encoder
Info: Found 2 design units, including 1 entities, in source file miller_decoder.vhd
    Info: Found design unit 1: miller_decoder-func
    Info: Found entity 1: miller_decoder
Info: Found 1 design units, including 1 entities, in source file miller.bdf
    Info: Found entity 1: miller
Info: Elaborating entity "miller_encoder" for the top level hierarchy
Info: Duplicate registers merged to single register
    Info (13350): Duplicate register "encodeout[1]~en" merged to single register "encodeout[0]~en"
Info: Implemented 12 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 2 output pins
    Info: Implemented 7 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Peak virtual memory: 179 megabytes
    Info: Processing ended: Thu May 14 00:25:33 2009
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02