miller.tan.rpt

使用VHDL实现基带码中密勒码的编解码

; N/A   ; None         ; 4.641 ns   ; en     ; sav2[0]           ; clk      ;
; N/A   ; None         ; 4.641 ns   ; en     ; sav2[1]           ; clk      ;
; N/A   ; None         ; 4.641 ns   ; en     ; sav1              ; clk      ;
; N/A   ; None         ; 4.460 ns   ; datain ; sav1              ; clk      ;
; N/A   ; None         ; 4.459 ns   ; datain ; sav2[0]           ; clk      ;
; N/A   ; None         ; 4.459 ns   ; datain ; sav2[1]           ; clk      ;
; N/A   ; None         ; 4.285 ns   ; datain ; encodeout[1]~reg0 ; clk      ;
; N/A   ; None         ; 4.284 ns   ; datain ; encodeout[0]~reg0 ; clk      ;
+-------+--------------+------------+--------+-------------------+----------+


+-----------------------------------------------------------------------------------+
; tco                                                                               ;
+-------+--------------+------------+-------------------+--------------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To           ; From Clock ;
+-------+--------------+------------+-------------------+--------------+------------+
; N/A   ; None         ; 5.761 ns   ; encodeout[1]~reg0 ; encodeout[1] ; clk        ;
; N/A   ; None         ; 5.752 ns   ; encodeout[0]~reg0 ; encodeout[0] ; clk        ;
; N/A   ; None         ; 5.702 ns   ; encodeout[0]~en   ; encodeout[1] ; clk        ;
; N/A   ; None         ; 5.692 ns   ; encodeout[0]~en   ; encodeout[0] ; clk        ;
+-------+--------------+------------+-------------------+--------------+------------+


+---------------------------------------------------------------------------------+
; th                                                                              ;
+---------------+-------------+-----------+--------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                ; To Clock ;
+---------------+-------------+-----------+--------+-------------------+----------+
; N/A           ; None        ; -4.054 ns ; datain ; encodeout[0]~reg0 ; clk      ;
; N/A           ; None        ; -4.055 ns ; datain ; encodeout[1]~reg0 ; clk      ;
; N/A           ; None        ; -4.229 ns ; datain ; sav2[0]           ; clk      ;
; N/A           ; None        ; -4.229 ns ; datain ; sav2[1]           ; clk      ;
; N/A           ; None        ; -4.230 ns ; datain ; sav1              ; clk      ;
; N/A           ; None        ; -4.411 ns ; en     ; sav2[0]           ; clk      ;
; N/A           ; None        ; -4.411 ns ; en     ; sav2[1]           ; clk      ;
; N/A           ; None        ; -4.411 ns ; en     ; sav1              ; clk      ;
+---------------+-------------+-----------+--------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Thu May 14 00:25:43 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off miller -c miller --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "sav2[1]" and destination register "encodeout[0]~reg0"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.619 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N15; Fanout = 6; REG Node = 'sav2[1]'
            Info: 2: + IC(0.315 ns) + CELL(0.419 ns) = 0.734 ns; Loc. = LCCOMB_X1_Y5_N28; Fanout = 3; COMB Node = 'encodeout[0]~488'
            Info: 3: + IC(0.225 ns) + CELL(0.660 ns) = 1.619 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'encodeout[0]~reg0'
            Info: Total cell delay = 1.079 ns ( 66.65 % )
            Info: Total interconnect delay = 0.540 ns ( 33.35 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.345 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'encodeout[0]~reg0'
                Info: Total cell delay = 1.526 ns ( 65.07 % )
                Info: Total interconnect delay = 0.819 ns ( 34.93 % )
            Info: - Longest clock path from clock "clk" to source register is 2.345 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N15; Fanout = 6; REG Node = 'sav2[1]'
                Info: Total cell delay = 1.526 ns ( 65.07 % )
                Info: Total interconnect delay = 0.819 ns ( 34.93 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "sav2[0]" (data pin = "en", clock pin = "clk") is 4.641 ns
    Info: + Longest pin to register delay is 7.022 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_60; Fanout = 4; PIN Node = 'en'
        Info: 2: + IC(5.512 ns) + CELL(0.660 ns) = 7.022 ns; Loc. = LCFF_X1_Y5_N19; Fanout = 6; REG Node = 'sav2[0]'
        Info: Total cell delay = 1.510 ns ( 21.50 % )
        Info: Total interconnect delay = 5.512 ns ( 78.50 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.345 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N19; Fanout = 6; REG Node = 'sav2[0]'
        Info: Total cell delay = 1.526 ns ( 65.07 % )
        Info: Total interconnect delay = 0.819 ns ( 34.93 % )
Info: tco from clock "clk" to destination pin "encodeout[1]" through register "encodeout[1]~reg0" is 5.761 ns
    Info: + Longest clock path from clock "clk" to source register is 2.345 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N21; Fanout = 1; REG Node = 'encodeout[1]~reg0'
        Info: Total cell delay = 1.526 ns ( 65.07 % )
        Info: Total interconnect delay = 0.819 ns ( 34.93 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.166 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N21; Fanout = 1; REG Node = 'encodeout[1]~reg0'
        Info: 2: + IC(0.514 ns) + CELL(2.652 ns) = 3.166 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'encodeout[1]'
        Info: Total cell delay = 2.652 ns ( 83.77 % )
        Info: Total interconnect delay = 0.514 ns ( 16.23 % )
Info: th for register "encodeout[0]~reg0" (data pin = "datain", clock pin = "clk") is -4.054 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.345 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'encodeout[0]~reg0'
        Info: Total cell delay = 1.526 ns ( 65.07 % )
        Info: Total interconnect delay = 0.819 ns ( 34.93 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 6.665 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_52; Fanout = 5; PIN Node = 'datain'
        Info: 2: + IC(5.456 ns) + CELL(0.275 ns) = 6.581 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 1; COMB Node = 'encodeout[0]~487'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.665 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'encodeout[0]~reg0'
        Info: Total cell delay = 1.209 ns ( 18.14 % )
        Info: Total interconnect delay = 5.456 ns ( 81.86 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 122 megabytes
    Info: Processing ended: Thu May 14 00:25:44 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01