miller.map.summary

使用VHDL实现基带码中密勒码的编解码

Analysis & Synthesis Status : Successful - Thu May 14 00:25:33 2009
Quartus II Version : 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
Revision Name : miller
Top-level Entity Name : miller_encoder
Family : Cyclone II
Total logic elements : 6
    Total combinational functions : 6
    Dedicated logic registers : 6
Total registers : 6
Total pins : 5
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0