mc8051_top.mrp

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Release 7.1i Map H.38
Xilinx Mapping Report File for Design 'mc8051_top'

Design Information
------------------
Command Line   : D:/Xilinx/bin/nt/map.exe -ise e:\vhdl\f8051\f8051.ise -intstyle
ise -p xc3s200-ft256-5 -cm area -pr b -k 4 -c 100 -o mc8051_top_map.ncd
mc8051_top.ngd mc8051_top.pcf 
Target Device  : xc3s200
Target Package : ft256
Target Speed   : -5
Mapper Version : spartan3 -- $Revision: 1.26.6.3 $
Mapped Date    : Thu Oct 25 20:45:29 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         590 out of   3,840   15%
  Number of 4 input LUTs:           2,730 out of   3,840   71%
Logic Distribution:
  Number of occupied Slices:                        1,583 out of   1,920   82%
    Number of Slices containing only related logic:   1,583 out of   1,583  100%
    Number of Slices containing unrelated logic:          0 out of   1,583    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          2,791 out of   3,840   72%
  Number used as logic:              2,730
  Number used as a route-thru:          45
  Number used for Dual Port RAMs:       16
    (Two LUTs used per Dual Port RAM)
  Number of bonded IOBs:               74 out of     173   42%
  Number of Block RAMs:                2 out of      12   16%
  Number of MULT18X18s:                1 out of      12    8%
  Number of GCLKs:                     2 out of       8   25%

Total equivalent gate count for design:  159,259
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  129 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network reset_c_i has no load.
WARNING:LIT:374 - The above warning message base_net_load_rule is repeated 29
   more times for the following (max. 5 shown):
   s_ram_wr,
   i_mc8051_rom/N1,
   i_mc8051_rom/N0,
   i_mc8051_ram/N0,
   i_mc8051_core/i_mc8051_control/i_control_mem/s_r0.I_8/SPO
   To see the details of these warning messages, please use the -detail switch.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_ibuf" (output signal=clk_c),
   BUFG symbol "i_mc8051_clockdiv/s_clk_pre_inferred_clock_cb" (output
   signal=s_clk_pre)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   1 block(s) removed
  15 block(s) optimized away

Section 5 - Removed Logic
-------------------------
Unused block "i_mc8051_ram/VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		i_mc8051_core/gen_mc8051_siu.0.i_mc8051_siu/GND
VCC 		i_mc8051_core/gen_mc8051_siu.0.i_mc8051_siu/VCC
GND 		i_mc8051_core/gen_mc8051_tmrctr.0.i_mc8051_tmrctr/GND
GND 		i_mc8051_core/i_mc8051_alu/gen_divider1.i_comb_divider/GND
VCC 		i_mc8051_core/i_mc8051_alu/gen_divider1.i_comb_divider/VCC
GND 		i_mc8051_core/i_mc8051_alu/gen_multiplier1.i_comb_mltplr/GND
VCC
		i_mc8051_core/i_mc8051_alu/i_addsub_core/gen_greater_four.gen_addsub.gen_addsu
b.4.gen_nibble_addsub.i_addsub_cy/VCC
GND
		i_mc8051_core/i_mc8051_alu/i_addsub_core/gen_greater_four.gen_addsub.gen_addsu
b.5.gen_last_addsub.i_addsub_ovcy/GND
VCC
		i_mc8051_core/i_mc8051_alu/i_addsub_core/gen_greater_four.gen_addsub.gen_addsu
b.5.gen_last_addsub.i_addsub_ovcy/VCC
GND 		i_mc8051_core/i_mc8051_alu/i_alucore/GND
GND 		i_mc8051_core/i_mc8051_control/i_control_mem/GND
VCC 		i_mc8051_core/i_mc8051_control/i_control_mem/VCC
GND 		i_mc8051_ram/GND
GND 		i_mc8051_rom/GND
VCC 		i_mc8051_rom/VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| all_rxd_i(0)                       | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| all_rxd_o(0)                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| all_rxdwr_o(0)                     | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| all_t0_i(0)                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| all_t1_i(0)                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| all_txd_o(0)                       | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| clk                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| int0_i(0)                          | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| int1_i(0)                          | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |