mc8051_top.mrp
来自「8051VHDL原代码」· MRP 代码 · 共 307 行 · 第 1/2 页
MRP
307 行
| p0_i(0) | IOB | INPUT | LVCMOS25 | | | | | || p0_i(1) | IOB | INPUT | LVCMOS25 | | | | | || p0_i(2) | IOB | INPUT | LVCMOS25 | | | | | || p0_i(3) | IOB | INPUT | LVCMOS25 | | | | | || p0_i(4) | IOB | INPUT | LVCMOS25 | | | | | || p0_i(5) | IOB | INPUT | LVCMOS25 | | | | | || p0_i(6) | IOB | INPUT | LVCMOS25 | | | | | || p0_i(7) | IOB | INPUT | LVCMOS25 | | | | | || p0_o(0) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p0_o(1) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p0_o(2) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p0_o(3) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p0_o(4) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p0_o(5) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p0_o(6) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p0_o(7) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p1_i(0) | IOB | INPUT | LVCMOS25 | | | | | || p1_i(1) | IOB | INPUT | LVCMOS25 | | | | | || p1_i(2) | IOB | INPUT | LVCMOS25 | | | | | || p1_i(3) | IOB | INPUT | LVCMOS25 | | | | | || p1_i(4) | IOB | INPUT | LVCMOS25 | | | | | || p1_i(5) | IOB | INPUT | LVCMOS25 | | | | | || p1_i(6) | IOB | INPUT | LVCMOS25 | | | | | || p1_i(7) | IOB | INPUT | LVCMOS25 | | | | | || p1_o(0) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p1_o(1) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p1_o(2) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p1_o(3) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p1_o(4) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p1_o(5) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p1_o(6) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p1_o(7) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p2_i(0) | IOB | INPUT | LVCMOS25 | | | | | || p2_i(1) | IOB | INPUT | LVCMOS25 | | | | | || p2_i(2) | IOB | INPUT | LVCMOS25 | | | | | || p2_i(3) | IOB | INPUT | LVCMOS25 | | | | | || p2_i(4) | IOB | INPUT | LVCMOS25 | | | | | || p2_i(5) | IOB | INPUT | LVCMOS25 | | | | | || p2_i(6) | IOB | INPUT | LVCMOS25 | | | | | || p2_i(7) | IOB | INPUT | LVCMOS25 | | | | | || p2_o(0) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p2_o(1) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p2_o(2) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p2_o(3) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p2_o(4) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p2_o(5) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p2_o(6) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p2_o(7) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p3_i(0) | IOB | INPUT | LVCMOS25 | | | | | || p3_i(1) | IOB | INPUT | LVCMOS25 | | | | | || p3_i(2) | IOB | INPUT | LVCMOS25 | | | | | || p3_i(3) | IOB | INPUT | LVCMOS25 | | | | | || p3_i(4) | IOB | INPUT | LVCMOS25 | | | | | || p3_i(5) | IOB | INPUT | LVCMOS25 | | | | | || p3_i(6) | IOB | INPUT | LVCMOS25 | | | | | || p3_i(7) | IOB | INPUT | LVCMOS25 | | | | | || p3_o(0) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p3_o(1) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p3_o(2) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p3_o(3) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p3_o(4) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p3_o(5) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p3_o(6) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || p3_o(7) | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || reset | IOB | INPUT | LVCMOS25 | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 74Number of Equivalent Gates for Design = 159,259Number of RPM Macros = 0Number of Hard Macros = 0DCIRESETs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DCMs = 0GCLKs = 2ICAPs = 018X18 Multipliers = 1Block RAMs = 2Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 162IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 74XORs = 140CARRY_INITs = 111CARRY_SKIPs = 0CARRY_MUXes = 200Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 8MUXFs = 311MULT_ANDs = 524 input LUTs used as Route-Thrus = 454 input LUTs = 2730Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 162Slice Flip Flops = 590SliceMs = 50SliceLs = 1533Slices = 1583Multiplier(8,8) = 1F6 Muxes = 56F5 Muxes = 228F8 Muxes = 6F7 Muxes = 21Xilinx Core blkmemsp_v6_2, Coregen 7.1.04i_ip3 = 2Number of LUT signals with 4 loads = 49Number of LUT signals with 3 loads = 101Number of LUT signals with 2 loads = 347Number of LUT signals with 1 load = 1869NGM Average fanout of LUT = 2.98NGM Maximum fanout of LUT = 94NGM Average fanin for LUT = 3.2766Number of LUT symbols = 2730⌨️ 快捷键说明
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