sanjiaobo.vhd

VHDL实现 SPWM 通过ADC1407转换实现变频控制和变幅控制； 通过LCD1602实现频率和调制比显示

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:13:07 04/17/2009 
-- Design Name: 
-- Module Name:    SANJIAOBO - RTL 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SANJIAOBO is
    Port ( CLK : in  STD_LOGIC;
           RESET : in  STD_LOGIC;
			  PUT_HZ:in integer range 0 to 255;
           SANJIAO_DATA : out  STD_LOGIC_VECTOR(7 downto 0));
end SANJIAOBO;

architecture RTL of SANJIAOBO is
signal TEMP :STD_LOGIC_VECTOR(7 downto 0);
signal UPDN: STD_LOGIC;
signal UNIT_HZ:integer range 0 to 1000000;
signal SIN_CLK:STD_LOGIC;
signal count_hz:integer range 0 to 100000;
signal cha:integer range 0 to 1000000;
signal PUT_HZ_integer:integer range 0 to 255;
begin
PUT_HZ_integer<=PUT_HZ;
--根据输入的频率算出脉冲个数；
process(CLK,PUT_HZ_integer)
begin
if rising_edge(CLK) then 
case (PUT_HZ_integer) is
WHEN 0 to 40  =>  UNIT_HZ <= 1943;   --频率为0-10HZ时，载波比为201；
WHEN 41 to 80 =>  UNIT_HZ  <= 2657;  --频率为10.25-20HZ时，载波比为147；
WHEN 81 to 120 => UNIT_HZ <= 3946;  --频率为20.25-30HZ?保?载波比为99；
WHEN 121 to 160 => UNIT_HZ <= 5661; --频率为30.25-40HZ时，载波???9；
WHEN 161 to 200 => UNIT_HZ <= 8681; --频率40.25-50HZ时，载波比为45；
WHEN 201 to 240 => UNIT_HZ <= 11837;  --频率为50.25-60HZ时，载波比为33；
WHEN others     => UNIT_HZ <= 11837;
end case;
end if;
end process;

process(PUT_HZ_integer,CLK,RESET)
begin
if RESET='0' then
count_hz<=1;
cha<=UNIT_HZ;
elsif rising_edge(CLK) then 
   if(cha>=PUT_HZ_integer) then
	  cha<=UNIT_HZ-count_hz*PUT_HZ_integer;
	  count_hz<=count_hz+1;
	  SIN_CLK<='0';
	else
	 count_hz<=1;
	 cha<=UNIT_HZ;
	 SIN_CLK<='1';
	 end if;
end if;
end process;



process(SIN_CLK,RESET)
begin
if RESET='0'then
   TEMP <="00000000";
	UPDN<='1';
elsif rising_edge(SIN_CLK) then
     if (UPDN='1')  then			
	    TEMP <=TEMP + 1;
		 if TEMP="11111110" then
       UPDN<= not UPDN ;
		 end if;
    elsif (UPDN='0') then
       TEMP <= TEMP - 1;
		 if TEMP="00000001" then
       UPDN<='1';
    end if;	 	
	 end if;   
end if;
end process;
SANJIAO_DATA <=TEMP;

end RTL;