comp.vhd

VHDL实现 SPWM 通过ADC1407转换实现变频控制和变幅控制； 通过LCD1602实现频率和调制比显示

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:56:18 04/17/2009 
-- Design Name: 
-- Module Name:    COMP - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity COMP is
    Port ( CLK : in  STD_LOGIC;
	        RESET : in  STD_LOGIC;	 
	        SANJIAO_DATA:in STD_LOGIC_VECTOR (7 downto 0);
			  A_Adjust:in STD_LOGIC_VECTOR (7 downto 0); 
			  B_Adjust:in STD_LOGIC_VECTOR (7 downto 0); 
			  C_Adjust:in STD_LOGIC_VECTOR (7 downto 0);		
			  A1_RESULT : out  STD_LOGIC;
           A2_RESULT : out  STD_LOGIC;
			  B1_RESULT : out  STD_LOGIC;
           B2_RESULT : out  STD_LOGIC;
			  C1_RESULT : out  STD_LOGIC;
           C2_RESULT : out  STD_LOGIC  
			  );
end COMP;

architecture RTL of COMP is
signal A_RESULT : STD_LOGIC;
signal B_RESULT : STD_LOGIC;
signal C_RESULT : STD_LOGIC;

begin
--得到A相脉冲
process(CLK,RESET)
begin
  if RESET='0'then
  A_RESULT <='0';
  elsif rising_edge(CLK) then
     if A_Adjust > SANJIAO_DATA then
	  A_RESULT <='1';
	  else 
	  A_RESULT <='0';
	  end if;
  end if;  
end process;
A1_RESULT <= A_RESULT;
A2_RESULT <= not A_RESULT;

--得到B相脉冲
process(CLK,RESET)
begin
  if RESET='0'then
  B_RESULT <='0';
  elsif rising_edge(CLK) then
     if B_Adjust > SANJIAO_DATA then
	  B_RESULT <='1';
	  else 
	  B_RESULT <='0';
	  end if;
  end if;  
end process;
B1_RESULT <= B_RESULT;
B2_RESULT <= not B_RESULT;

--得到C相脉冲
process(CLK,RESET)
begin
  if RESET='0'then
  C_RESULT <='0';
  elsif rising_edge(CLK) then
     if C_Adjust > SANJIAO_DATA then
	  C_RESULT <='1';
	  else 
	  C_RESULT <='0';
	  end if;
  end if;  
end process;
C1_RESULT <= C_RESULT;
C2_RESULT <= not C_RESULT;

end RTL;