spwm_adc_lcd_tb.vhd

VHDL实现 SPWM 通过ADC1407转换实现变频控制和变幅控制； 通过LCD1602实现频率和调制比显示

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-- Company: 
-- Engineer:
--
-- Create Date:   23:53:48 05/16/2009
-- Design Name:   
-- Module Name:   G:/SPWM_ADC_LCD/SPWM_ADC_LCD_TB.vhd
-- Project Name:  SPWM_ADC_LCD
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: SPWM_ADC_LCD
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY SPWM_ADC_LCD_TB IS
END SPWM_ADC_LCD_TB;
 
ARCHITECTURE behavior OF SPWM_ADC_LCD_TB IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT SPWM_ADC_LCD
    PORT(
         CLK : IN  std_logic;
         RESET : IN  std_logic;
         A1_RESULT : OUT  std_logic;
         A2_RESULT : OUT  std_logic;
         B1_RESULT : OUT  std_logic;
         B2_RESULT : OUT  std_logic;
         C1_RESULT : OUT  std_logic;
         C2_RESULT : OUT  std_logic;
         LCD_RS : OUT  std_logic;
         LCD_RW : OUT  std_logic;
         LCD_EN : OUT  std_logic;
         FLASH_CE : OUT  std_logic;
         data : OUT  std_logic_vector(3 downto 0);
         SPI_MOSI : OUT  std_logic;
         AMP_CS : OUT  std_logic;
         SPI_SCK : OUT  std_logic;
         AMP_SHDN : OUT  std_logic;
         AD_CONV : OUT  std_logic;
         AMP_OUT : IN  std_logic;
         SPI_SS_B : OUT  std_logic;
         DAC_CS : OUT  std_logic;
         SF_CE0 : OUT  std_logic;
         SPI_MISO : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal RESET : std_logic := '0';
   signal AMP_OUT : std_logic := '0';
   signal SPI_MISO : std_logic := '0';

 	--Outputs
   signal A1_RESULT : std_logic;
   signal A2_RESULT : std_logic;
   signal B1_RESULT : std_logic;
   signal B2_RESULT : std_logic;
   signal C1_RESULT : std_logic;
   signal C2_RESULT : std_logic;
   signal LCD_RS : std_logic;
   signal LCD_RW : std_logic;
   signal LCD_EN : std_logic;
   signal FLASH_CE : std_logic;
   signal data : std_logic_vector(3 downto 0);
   signal SPI_MOSI : std_logic;
   signal AMP_CS : std_logic;
   signal SPI_SCK : std_logic;
   signal AMP_SHDN : std_logic;
   signal AD_CONV : std_logic;
   signal SPI_SS_B : std_logic;
   signal DAC_CS : std_logic;
   signal SF_CE0 : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: SPWM_ADC_LCD PORT MAP (
          CLK => CLK,
          RESET => RESET,
          A1_RESULT => A1_RESULT,
          A2_RESULT => A2_RESULT,
          B1_RESULT => B1_RESULT,
          B2_RESULT => B2_RESULT,
          C1_RESULT => C1_RESULT,
          C2_RESULT => C2_RESULT,
          LCD_RS => LCD_RS,
          LCD_RW => LCD_RW,
          LCD_EN => LCD_EN,
          FLASH_CE => FLASH_CE,
          data => data,
          SPI_MOSI => SPI_MOSI,
          AMP_CS => AMP_CS,
          SPI_SCK => SPI_SCK,
          AMP_SHDN => AMP_SHDN,
          AD_CONV => AD_CONV,
          AMP_OUT => AMP_OUT,
          SPI_SS_B => SPI_SS_B,
          DAC_CS => DAC_CS,
          SF_CE0 => SF_CE0,
          SPI_MISO => SPI_MISO
        );
 
    CLK<= NOT CLK after 10 ns;
RESET <='1','0'after 15 ns,'1' after 50 ns;

END;