spwm_adc_lcd.vhd

VHDL实现 SPWM 通过ADC1407转换实现变频控制和变幅控制； 通过LCD1602实现频率和调制比显示

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:14:04 05/14/2009 
-- Design Name: 
-- Module Name:    SPWM_ADC_LCD - RTL 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SPWM_ADC_LCD is
    Port ( CLK : in  STD_LOGIC;
           RESET : in  STD_LOGIC;
  			  A1_RESULT : out  STD_LOGIC;
           A2_RESULT : out  STD_LOGIC;
			  B1_RESULT : out  STD_LOGIC;
           B2_RESULT : out  STD_LOGIC;
			  C1_RESULT : out  STD_LOGIC;
           C2_RESULT : out  STD_LOGIC;
			  
			  LCD_RS : out std_logic;
           LCD_RW : out std_logic;
           LCD_EN : out std_logic;
	        FLASH_CE:out std_logic;
           data : out std_logic_vector(3 downto 0);
			  
			  SPI_MOSI : out  STD_LOGIC;
           AMP_CS : out  STD_LOGIC;
           SPI_SCK : out  STD_LOGIC;
           AMP_SHDN : out  STD_LOGIC;
           AD_CONV : out  STD_LOGIC;
           AMP_OUT : in  STD_LOGIC;
		     SPI_SS_B :out STD_LOGIC;
	        DAC_CS :out STD_LOGIC;
		     SF_CE0 :out STD_LOGIC;
           SPI_MISO : in  STD_LOGIC);

end SPWM_ADC_LCD;

architecture RTL of SPWM_ADC_LCD is

	COMPONENT SPWM
    Port ( CLK : in  STD_LOGIC;
           RESET : in  STD_LOGIC;
			  PUT_HZ:in integer range 0 to 255;
			  PUT_ff:in integer range 0 to 255;
  			  A1_RESULT : out  STD_LOGIC;
           A2_RESULT : out  STD_LOGIC;
			  B1_RESULT : out  STD_LOGIC;
           B2_RESULT : out  STD_LOGIC;
			  C1_RESULT : out  STD_LOGIC;
           C2_RESULT : out  STD_LOGIC);
	END COMPONENT;

	COMPONENT LCD
    Port ( ADC_OUT_HZ:in INTEGER RANGE 0 to 255;
           ADC_OUT_ff:in INTEGER RANGE 0 to 255;
           CLK : in std_logic;
           Reset : in std_logic;  
           LCD_RS : out std_logic;
           LCD_RW : out std_logic;
           LCD_EN : out std_logic;
	        FLASH_CE:out std_logic;
           data : out std_logic_vector(3 downto 0));
    END COMPONENT;
	 
	 COMPONENT ADC_HZ
    Port ( CLK : in  STD_LOGIC;
           SPI_MOSI : out  STD_LOGIC;
           AMP_CS : out  STD_LOGIC;
           SPI_SCK : out  STD_LOGIC;
           AMP_SHDN : out  STD_LOGIC;
           AD_CONV : out  STD_LOGIC;
			  ADC_OUT_ff: out INTEGER range 0 TO 255;
			  ADC_OUT_HZ : out  INTEGER range 0 TO 255;
			  RESET:in STD_LOGIC;
           AMP_OUT : in  STD_LOGIC;
		     SPI_SS_B :out STD_LOGIC;
	        DAC_CS :out STD_LOGIC;
		     SF_CE0 :out STD_LOGIC;
           SPI_MISO : in  STD_LOGIC);
   END COMPONENT;
signal PUT_HZ: integer range 0 to 255;
signal PUT_ff: integer range 0 to 255;




begin
	Inst_SPWM: SPWM PORT MAP(
		CLK => CLK,
		RESET =>RESET,
		PUT_HZ =>PUT_HZ,
		PUT_ff =>PUT_ff,
		A1_RESULT => A1_RESULT,
		A2_RESULT => A2_RESULT,
		B1_RESULT => B1_RESULT,
		B2_RESULT => B2_RESULT,
		C1_RESULT => C1_RESULT,
		C2_RESULT => C2_RESULT
	);

	Inst_LCD: LCD PORT MAP(
		CLK => CLK,
		RESET =>RESET,
		ADC_OUT_HZ =>PUT_HZ,
		ADC_OUT_ff =>PUT_ff,
		LCD_RS => LCD_RS,
		LCD_RW => LCD_RW,
		LCD_EN => LCD_EN,
		FLASH_CE => FLASH_CE,
		data => data
	);
	
	Inst_ADC_HZ: ADC_HZ PORT MAP(
		CLK => CLK,
		RESET =>RESET,
		ADC_OUT_HZ =>PUT_HZ,
		ADC_OUT_ff =>PUT_ff,
		SPI_MOSI => SPI_MOSI,
		AMP_CS => AMP_CS,
		SPI_SCK => SPI_SCK,
		AMP_SHDN => AMP_SHDN,
		AD_CONV => AD_CONV,
		AMP_OUT => AMP_OUT,
		SPI_SS_B => SPI_SS_B,
		DAC_CS => DAC_CS,
		SF_CE0 => SF_CE0,
		SPI_MISO => SPI_MISO
	);	


end RTL;