lcd.vhd

VHDL实现 SPWM 通过ADC1407转换实现变频控制和变幅控制； 通过LCD1602实现频率和调制比显示

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:14:00 05/05/2009 
-- Design Name: 
-- Module Name:    LCD - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD is
Port ( ADC_OUT_HZ:in INTEGER RANGE 0 to 255;
       ADC_OUT_ff:in INTEGER RANGE 0 to 255;
        CLK : in std_logic;
       Reset : in std_logic;  
     LCD_RS : out std_logic;
     LCD_RW : out std_logic;
     LCD_EN : out std_logic;
	  FLASH_CE:out std_logic;
        data : out std_logic_vector(3 downto 0));
end LCD;
architecture RTL of LCD is
type iState is ( 
             Write_instr,   --写命令字
         Write_DataUP4_1,   --写LCD?幌??4位
       Write_DataDown4_1,   --写LCD一线低4位
        Set_DDRamAddUp,   --设置DDRam地址????  
      Set_DDRamAddDown,   --设置DDRam地址低4位
        Write_DataUP4_2,    --写LCD二线高4位
       Write_DataDown4_2    --写LCD二线低4位
    );
  
signal State:iState; 
type Ram is array(0 to 15) of std_logic_vector(7 downto 0);
constant  MyRamUp:Ram:=(x"20",x"20",x"20",x"66",x"20",x"20",x"20",x"20",x"20",x"E0",x"20",x"20",x"20",x"e2",x"20",x"20"); 
              --The frequenry is 
--constant MyRamDown:Ram:=(x"20",x"20",x"46",x"50",x"47",x"41",x"20",x"50",x"72",x"6f",x"67",x"72",x"61",x"6d",x"20",x"20"); 
              --FPGA Program
signal LCD_Clk : std_logic:='0';
signal datacnt : integer range 0 to 15:=0; 
signal MyRamDown:RAM;
signal A:INTEGER range 0 to 255;
signal B:INTEGER range 0 to 255; 
signal A_SIG:std_logic_vector(1 downto 0);
signal B_SIG:std_logic_vector(5 downto 0);
signal ADC_OUT_HZ_SIG: std_logic_vector(7 downto 0);
begin
LCD_RW <= '0';
FLASH_CE <= '1';
LCD_EN <= LCD_Clk; 
ADC_OUT_HZ_SIG <= conv_STD_LOGIC_VECTOR (ADC_OUT_HZ,8);
A_SIG<=ADC_OUT_HZ_SIG(1 downto 0);
A<=conv_integer(A_SIG);

B_SIG<=ADC_OUT_HZ_SIG(7 downto 2);
B<=conv_integer(B_SIG);

process(reset, CLK)
begin
if rising_edge(CLK) then 
case (A) is
WHEN 0 => MyRamDown(3) <= x"30";MyRamDown(4) <= x"30";
WHEN 1 => MyRamDown(3) <= x"32";MyRamDown(4) <= x"35";
WHEN 2 => MyRamDown(3) <= x"35";MyRamDown(4) <= x"30";
WHEN 3 => MyRamDown(3) <= x"37";MyRamDown(4) <= x"35";
WHEN OTHERS => MyRamDown(3) <= x"20";MyRamDown(4) <= x"20";
end case;

case (B) is
WHEN 0|10|20|30|40|50|60 => MyRamDown(1) <= x"30";
WHEN 1|11|21|31|41|51    => MyRamDown(1) <= x"31";
WHEN 2|12|22|32|42|52    => MyRamDown(1) <= x"32";
WHEN 3|13|23|33|43|53    => MyRamDown(1) <= x"33";
WHEN 4|14|24|34|44|54    => MyRamDown(1) <= x"34";
WHEN 5|15|25|35|45|55    => MyRamDown(1) <= x"35";
WHEN 6|16|26|36|46|56    => MyRamDown(1) <= x"36";
WHEN 7|17|27|37|47|57    => MyRamDown(1) <= x"37";
WHEN 8|18|28|38|48|58    => MyRamDown(1) <= x"38";
WHEN 9|19|29|39|49|59    => MyRamDown(1) <= x"39";
WHEN OTHERS => MyRamDown(1) <= x"20";
end case;

case (B) is
WHEN 0 to 9 => MyRamDown(0) <= x"30";
WHEN 10 to 19 => MyRamDown(0) <= x"31";
WHEN 20 to 29 => MyRamDown(0) <= x"32";
WHEN 30 to 39 => MyRamDown(0) <= x"33";
WHEN 40 to 49 => MyRamDown(0) <= x"34";
WHEN 50 to 59 => MyRamDown(0) <= x"35";
WHEN 60 => MyRamDown(0) <= x"36";
WHEN OTHERS => MyRamDown(0) <= x"20";
end case;

MyRamDown(2) <= x"A5";
MyRamDown(5) <= x"48";
MyRamDown(6) <= x"5A";
MyRamDown(7) <= x"20";

MyRamDown(11) <= x"20";


MyRamDown(13) <= x"A5";

end if;
end process;




process(reset, CLK)
begin
if rising_edge(CLK) then 
case (ADC_OUT_HZ) is
WHEN 1 to 40 => MyRamDown(8) <= x"32";MyRamDown(9) <= x"30";MyRamDown(10) <= x"31";
WHEN 41 to 80 => MyRamDown(8) <= x"31";MyRamDown(9) <= x"34";MyRamDown(10) <= x"37";
WHEN 81 to 120 => MyRamDown(8) <= x"20";MyRamDown(9) <= x"39";MyRamDown(10) <= x"39";
WHEN 121 to 160 => MyRamDown(8) <= x"20";MyRamDown(9) <= x"36";MyRamDown(10) <= x"39";
WHEN 161 to 200 => MyRamDown(8) <= x"20";MyRamDown(9) <= x"34";MyRamDown(10) <= x"35";
WHEN 201 to 240 => MyRamDown(8) <= x"20";MyRamDown(9) <= x"33";MyRamDown(10) <= x"33";
WHEN others     => MyRamDown(8) <= x"20";MyRamDown(9) <= x"33";MyRamDown(10) <= x"33";
END CASE;
END IF;
END process;


process(reset, CLK)
begin
if rising_edge(CLK) then 
case (ADC_OUT_ff) is
WHEN 1 to 13 => MyRamDown(12)  <= x"30";MyRamDown(14) <= x"30";MyRamDown(15) <= x"35";
WHEN 14 to 26 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"31";MyRamDown(15) <= x"30";
WHEN 27 to 38 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"31";MyRamDown(15) <= x"35";
WHEN 39 to 51 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"32";MyRamDown(15) <= x"30";
WHEN 52 to 64 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"32";MyRamDown(15) <= x"35";
WHEN 65 to 77 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"33";MyRamDown(15) <= x"30";
WHEN 78 to 89 => MyRamDown(12)  <= x"30";MyRamDown(14) <= x"33";MyRamDown(15) <= x"35";
WHEN 90 to 102 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"34";MyRamDown(15) <= x"30";
WHEN 103 to 115 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"34";MyRamDown(15) <= x"35";
WHEN 116 to 128 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"35";MyRamDown(15) <= x"30";
WHEN 129 to 140 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"35";MyRamDown(15) <= x"35";
WHEN 141 to 153 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"36";MyRamDown(15) <= x"30";
WHEN 154 to 166 => MyRamDown(12)  <= x"30";MyRamDown(14) <= x"36";MyRamDown(15) <= x"35";
WHEN 167 to 179 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"37";MyRamDown(15) <= x"30";
WHEN 180 to 191 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"37";MyRamDown(15) <= x"35";
WHEN 192 to 204 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"38";MyRamDown(15) <= x"30";
WHEN 205 to 217 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"38";MyRamDown(15) <= x"35";
WHEN 218 to 230 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"39";MyRamDown(15) <= x"30";
WHEN 231 to 242 => MyRamDown(12) <= x"30";MyRamDown(14) <= x"39";MyRamDown(15) <= x"35";
WHEN 243 to 255 => MyRamDown(12) <= x"31";MyRamDown(14) <= x"30";MyRamDown(15) <= x"30";
WHEN others     => MyRamDown(12) <= x"31";MyRamDown(14) <= x"30";MyRamDown(15) <= x"30";
END CASE;
END IF;
END process;

process(CLK)                     --20000分频,满足时序要??
variable n1:integer range 0 to 19999;
begin 
if (Reset='0') then
   n1:=0;
   LCD_Clk<='0';
  elsif rising_edge(CLK) then
  if n1<19999 then
    n1:=n1+1;
  else 
    n1:=0;
    LCD_Clk<=not LCD_Clk;
  end if;
end if;
end process;

process(LCD_Clk,state,reset)
begin
if Reset='0'  then
	datacnt<=0;
   state<=Write_instr;
   LCD_RS <='0';
elsif rising_edge(LCD_Clk) then
   case state is

  when Write_instr=>       --写命令字到LCD控制器 
   LCD_RS<='0';            
   if(datacnt=0)then
    data<="0011";        --0011
    datacnt<=datacnt+1;
   elsif(datacnt=1)then
    data<="0011";        --0011
    datacnt<=datacnt+1;
   elsif(datacnt=2)then
    data<="0011";        --0011
    datacnt<=datacnt+1;
   elsif(datacnt=3)then
    data<="0010";        --0010
    datacnt<=datacnt+1; 
   elsif(datacnt=4)then      --0x28 :  0010 1000 =>功能设置
    data<="0010";
    datacnt<=datacnt+1;
   elsif(datacnt=5)then
    data<="1000";
    datacnt<=datacnt+1; 
   elsif(datacnt=6)then      --0x06 :  0000 0110 =>模式设定
    data<="0000";
    datacnt<=datacnt+1;
   elsif(datacnt=7)then
    data<="0110";
    datacnt<=datacnt+1;
   elsif(datacnt=8)then     --0x0c :  0000 1100 =>显示设定
    data<="0000";
    datacnt<=datacnt+1;
   elsif(datacnt=9)then
    data<="1100";
    datacnt<=datacnt+1;  
   elsif(datacnt=10)then    --0x10 : 1000 0000 =>00H 设定读写地址位
    data<="1000";
    datacnt<=datacnt+1;
   else
    data<="0000";
    datacnt<=0;
    state<=Write_DataUP4_1;
   end if;

	
	
  when Write_DataUP4_1=>
   LCD_RS<='1';   
   data <= MyRamUp(datacnt)(7 downto 4);
   state <= Write_DataDown4_1; 
   
  when Write_DataDown4_1=>
   if datacnt=15 then
    data <= MyRamUp(datacnt)(3 downto 0);
    datacnt<=0;
    state <=Set_DDRamAddUp;
   else
    data <= MyRamUp(datacnt)(3 downto 0);
    datacnt<=datacnt+1;
    state <=Write_DataUP4_1;
   end if;
   
  when Set_DDRamAddUp=> --0xc0 : 1100 0000=>40H 设定读写地址位
    LCD_RS<='0';
    data<="1100";
    state<=Set_DDRamAddDown;
   
  when Set_DDRamAddDown=>
    data<="0000";
    state<=Write_DataUP4_2;
   
  when Write_DataUP4_2=>
    LCD_RS<='1';   
    data <= MyRamDown(datacnt)(7 downto 4);
    state <= Write_DataDown4_2; 
   
  when Write_DataDown4_2=>
    if datacnt=15 then
     data <= MyRamDown(datacnt)(3 downto 0);
     datacnt<=0;
     state <=Write_DataUP4_1;
    else
     data <= MyRamDown(datacnt)(3 downto 0);
     datacnt<=datacnt+1;
     state <=Write_DataUP4_2;
    end if;
   
  when others=>
    state<=Write_instr;
   
  end case;
  end if;
end process;
end RTL;