divhz.vhd

来自「VHDL实现 SPWM 通过ADC1407转换实现变频控制和变幅控制； 通过」· VHDL 代码 · 共 83 行

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:45:01 04/22/2009 
-- Design Name: 
-- Module Name:    DIVHZ - RTL 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DIVHZ is

port(CLK:IN STD_LOGIC;
     RESET:IN STD_LOGIC;
	  CLKOUT:OUT STD_LOGIC
);
		
end DIVHZ;

architecture RTL of DIVHZ is
signal s1 : std_logic;
signal s2 : std_logic;
signal cnt : integer range  0 to 5;

begin
process(RESET,CLK)
begin
if reset='0' then
   cnt<=0;
elsif clk'event and clk='1' then
   if cnt=5 then
   	cnt<=0;
   else cnt <= cnt+1;
	end if;
end if;
end process;

process(RESET,CLK)
begin
if reset='0' then
   s1<='0';
elsif clk'event and clk='1' then
   if cnt=0 then
   	s1<= not s1;
	else s1<= s1;
	end if;
end if;
end process;

process(RESET,CLK)
begin
if reset='0' then
   s2<='1';
elsif clk'event and clk='0' then
   if cnt=3 then
      s2<= not s2;
   else s2 <=s2;
	end if;
end if;
end process;
CLKOUT <= s1 xor s2; 
end RTL;