adc_hz.vhd

VHDL实现ADC1407模数转换。 ADC_HZ为顶层文件。

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:11:54 04/22/2009 
-- Design Name: 
-- Module Name:    ADC_HZ - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADC_HZ is

 Port ( CLK : in  STD_LOGIC;
           SPI_MOSI : out  STD_LOGIC;
           AMP_CS : out  STD_LOGIC;
           SPI_SCK : out  STD_LOGIC;
           AMP_SHDN : out  STD_LOGIC;
           AD_CONV : out  STD_LOGIC;
			  ADC_OUT:out STD_LOGIC_VECTOR (7 downto 0);
			  OUT_HZ : out  INTEGER range 0 TO 255;
			  RESET:in STD_LOGIC;
           AMP_OUT : in  STD_LOGIC;
		     SPI_SS_B :out STD_LOGIC;
	        DAC_CS :out STD_LOGIC;
		     SF_CE0 :out STD_LOGIC;
           SPI_MISO : in  STD_LOGIC);
end ADC_HZ;

architecture RTL of ADC_HZ is

	COMPONENT DIVHZ
	PORT(
		CLK : IN std_logic;
		RESET : IN std_logic;          
		CLKOUT : OUT std_logic
		);
	END COMPONENT;
	
	
	COMPONENT ADC
	PORT(
		CLK : IN std_logic;
		RESET : IN std_logic;
		AMP_OUT : in  STD_LOGIC;
		SPI_MISO : IN std_logic;          
		SPI_MOSI : OUT std_logic;
		AMP_CS : OUT std_logic;
		SPI_SCK : OUT std_logic;
		AMP_SHDN : OUT std_logic;
		AD_CONV : OUT std_logic;
		SPI_SS_B :out STD_LOGIC;
	   DAC_CS :out STD_LOGIC;
		SF_CE0 :out STD_LOGIC;
		ADC_OUT :OUT std_logic_vector(7 downto 0);
		OUT_HZ : out  INTEGER range 0 TO 255
		);
	END COMPONENT;
	
signal CLK_SIG:  std_logic;




begin

	Inst_DIVHZ: DIVHZ PORT MAP(
		CLK => CLK ,
		RESET =>RESET ,
		CLKOUT => CLK_SIG
	);
	
	
	
		Inst_ADC: ADC PORT MAP(
		CLK => CLK_SIG,
		SPI_MOSI =>SPI_MOSI ,
		AMP_CS =>AMP_CS ,
		SPI_SCK =>SPI_SCK ,
		AMP_SHDN =>AMP_SHDN ,
		AD_CONV =>AD_CONV ,
		ADC_OUT =>ADC_OUT ,
		OUT_HZ => OUT_HZ,
		RESET => RESET,
		AMP_OUT => AMP_OUT,
		SPI_MISO =>SPI_MISO ,
		SPI_SS_B =>SPI_SS_B ,
		DAC_CS => DAC_CS ,
		SF_CE0 => SF_CE0
	);

end RTL;