adc.vhd

VHDL实现ADC1407模数转换。 ADC_HZ为顶层文件。

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:55:28 04/20/2009 
-- Design Name: 
-- Module Name:    ADC - RTL 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADC is
    Port ( CLK : in  STD_LOGIC;
           SPI_MOSI : out  STD_LOGIC;
           AMP_CS : out  STD_LOGIC;
           SPI_SCK : out  STD_LOGIC;
           AMP_SHDN : out  STD_LOGIC;
           AD_CONV : out  STD_LOGIC;
			  ADC_OUT_ff: out INTEGER range 1 TO 255;
			  ADC_OUT_HZ : out  INTEGER range 1 TO 240;
			  RESET:in STD_LOGIC;
           AMP_OUT : in  STD_LOGIC;
			  SPI_MISO : in  STD_LOGIC;
			  SPI_SS_B :out STD_LOGIC;
			  DAC_CS :out STD_LOGIC;
			  SF_CE0 :out STD_LOGIC
			  );

end ADC;

architecture RTL of ADC is

TYPE STATE is (start,transfer,end_transfer,sta_convert,convert);
signal current_state, next_state : state; 
signal COUN_HZ: STD_LOGIC_VECTOR (3 downto 0);
signal CS: STD_LOGIC;
signal CONV:STD_LOGIC;
signal GAIN: STD_LOGIC_VECTOR (7 downto 0);
signal COUN_MC: STD_LOGIC_VECTOR (7 downto 0);
signal CN_0: STD_LOGIC_VECTOR (13 downto 0);
signal CN_1: STD_LOGIC_VECTOR (13 downto 0);
signal con_sck:STD_LOGIC;
signal ADC_OUT_HZ_sig: STD_LOGIC_VECTOR (7 downto 0);
signal ADC_OUT_ff_sig: STD_LOGIC_VECTOR (7 downto 0);




begin
SPI_SS_B<='1';
DAC_CS<='1';
SF_CE0<='1';
AMP_SHDN <='0';
 sync :process(RESET,clk) 
 begin 
  if(reset = '0') then 
   current_state <= start; 
  elsif(clk'event and clk = '0') then 
   current_state <= next_state; 
  end if; 
 end process sync; 
 
  comb :process(current_state,COUN_HZ,COUN_MC) 
 begin 
  case current_state is 
   when start =>  
    next_state <= transfer; 
	 CS <= '1'; 
    CONV <= '0'; 
	 con_sck <='0';
   when transfer =>  
	if(COUN_HZ < "1000") then
    next_state <= transfer; 
	else 
	 next_state <= end_transfer; 
	end if;
	 CS <= '0'; 
    CONV <= '0'; 
	 con_sck <='1';

   when end_transfer =>  
    next_state <= sta_convert; 
	 CS <= '1'; 
    CONV <= '0'; 
	 con_sck <='0';

	 
   when sta_convert =>  
    next_state <= convert; 
	 CS <= '1'; 
    CONV <= '1'; 
	 con_sck <='0';
	 
   when convert => 
	if(COUN_MC ="00100010") then
	 next_state <= sta_convert; 	 
	else 
	 next_state <= convert; 
	end if;
	CS <= '1'; 
   CONV <= '0'; 	
	con_sck <='1';	 
	
   when others =>
	next_state <= start; 
   CS <= '1'; 
   CONV <= '0'; 
	con_sck <='0';
  end case;
   AMP_CS <= CS;
   AD_CONV <=CONV; 
   end process comb; 



process(CLK,RESET)
begin
if RESET<='0' then 
   COUN_MC <="00000000";
	CN_0 <="00000000000000";
elsif CLK ' event and CLK ='1' then
 if(current_state = convert) then
   if (COUN_MC = "00100010") then
       COUN_MC <="00000001";
   else case CONV_INTEGER(COUN_MC) is
   when 2 to 16 =>   CN_0 <=CN_0(12 downto 0) &SPI_MISO; COUN_MC <= COUN_MC+1;
	when 19 to 32 =>  CN_1 <=CN_1(12 downto 0) &SPI_MISO; COUN_MC <= COUN_MC+1;
	when others => COUN_MC <= COUN_MC+1;
   end case;
	end if;
 end if;
end if;	
 if(COUN_MC = "00100010") then
   if(CN_0>"01111111100000") then
   ADC_OUT_hz_sig <= "11111111";
	elsif(CN_0<"00000000011111") then
	ADC_OUT_hz_sig <= "00000000";
	else 
	ADC_OUT_hz_sig <=CN_0(12 downto 5);
	end if;
	
   if(CN_1>"01111111100000") then
   ADC_OUT_ff_sig <= "11111111";
	elsif(CN_1<"00000000011111") then
	ADC_OUT_ff_sig <= "00000001";
	else 
	ADC_OUT_ff_sig <=CN_1(12 downto 5);
	end if;
	
end if;
end process;

--对数据进行处理，以符合输入频率的要求；1-240
process(CLK,RESET)
begin
if rising_edge(CLK) then
 if(ADC_OUT_hz_sig>"11110000") then
   ADC_OUT_HZ<=240;
 elsif(ADC_OUT_hz_sig<"00000001")then
  ADC_OUT_HZ<=1;
 else  ADC_OUT_HZ<=conv_integer(ADC_OUT_HZ_sig);
 end if;
 ADC_OUT_ff<=conv_integer(ADC_OUT_ff_sig);
end if; 
end process;


	

--发送增益；
process(CLK,RESET)
begin
if RESET<='0' then  
   GAIN <="00100011";
	COUN_HZ<="0000";
	SPI_MOSI<='0';
elsif CLK ' event and CLK ='0' then 
   if(CS = '0') then
   if(COUN_HZ < "1000") then
      SPI_MOSI <= GAIN(7);
      GAIN <=GAIN(6 downto 0) &'0';
	   COUN_HZ<=COUN_HZ+1;
	else COUN_HZ<=COUN_HZ+1;
    end if;
	 end if;
end if;
end process;


SPI_SCK <= con_sck and CLK;
end RTL;