adc_hz_tb.vhd

VHDL实现ADC1407模数转换。 ADC_HZ为顶层文件。

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-- Company: 
-- Engineer:
--
-- Create Date:   15:18:02 04/29/2009
-- Design Name:   
-- Module Name:   G:/PRO/AD/adc_hz_tb.vhd
-- Project Name:  AD
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ADC_HZ
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY adc_hz_tb IS
END adc_hz_tb;
 
ARCHITECTURE behavior OF adc_hz_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ADC_HZ
    PORT(
         CLK : IN  std_logic;
         SPI_MOSI : OUT  std_logic;
         AMP_CS : OUT  std_logic;
         SPI_SCK : OUT  std_logic;
         AMP_SHDN : OUT  std_logic;
         AD_CONV : OUT  std_logic;
         OUT_HZ : OUT  std_logic_vector(13 downto 0);
         RESET : IN  std_logic;
         AMP_OUT : IN  std_logic;
         CS_GAI : OUT  std_logic_vector(7 downto 0);
         SPI_MISO : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal RESET : std_logic := '0';
   signal AMP_OUT : std_logic := '0';
   signal SPI_MISO : std_logic := '0';

 	--Outputs
   signal SPI_MOSI : std_logic;
   signal AMP_CS : std_logic;
   signal SPI_SCK : std_logic;
   signal AMP_SHDN : std_logic;
   signal AD_CONV : std_logic;
   signal OUT_HZ : std_logic_vector(13 downto 0);
   signal CS_GAI : std_logic_vector(7 downto 0);
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ADC_HZ PORT MAP (
          CLK => CLK,
          SPI_MOSI => SPI_MOSI,
          AMP_CS => AMP_CS,
          SPI_SCK => SPI_SCK,
          AMP_SHDN => AMP_SHDN,
          AD_CONV => AD_CONV,
          OUT_HZ => OUT_HZ,
          RESET => RESET,
          AMP_OUT => AMP_OUT,
          CS_GAI => CS_GAI,
          SPI_MISO => SPI_MISO
        );
 
  RESET<='1','0' after 15 ns,'1' after 100 ns,'0' after 19000 ns,'1' after 20000 ns;
CLK<=not CLK after 10 ns;
SPI_MISO <='1','0' after 4500 ns;

END;