zhuanpan.vhd

增量式光电编码器输出四分频脉冲计数

-- GAL16.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity gal16 is
    port(   pos_in, neg_in: in std_logic;
            clockh,clockl, reset:   in std_logic;
            error:  out std_logic;
            updown,pulse:out std_logic
            --pos_out: out std_logic_vector(23 downto 0)
            );
end gal16;

architecture gal16_arch of gal16 is

--signal  pre_state, cur_state: std_logic_vector(1 downto 0);
signal  Spulse:  std_logic;
begin

gal16_proc: process( pos_in, neg_in,clockl,reset)
variable temp_err,Vupdown:std_logic;
variable  pre_state, cur_state: std_logic_vector(1 downto 0);
        begin    
            cur_state(0) := neg_in;
            cur_state(1) := pos_in;                
            if (reset = '0') then                                
                pre_state(0) := neg_in;  
                pre_state(1) := pos_in;

                Vupdown:='1';
                temp_err := '0';
                Spulse<='0';
            else
                if(rising_edge(clockl)) then
                    --cur_state(0) := neg_in;
                    --cur_state(1) := pos_in;   
                                  
                    if(( pre_state = "00" and cur_state = "10") or
                       ( pre_state = "01" and cur_state = "00") or
                       ( pre_state = "10" and cur_state = "11") or
                       ( pre_state = "11" and cur_state = "01")) then                      
                       Vupdown:='1';
                       Spulse<='1';
                    elsif(( pre_state = "00" and cur_state = "01") or
                       ( pre_state = "01" and cur_state = "11") or
                       ( pre_state = "10" and cur_state = "00") or
                       ( pre_state = "11" and cur_state = "10")) then
                        Vupdown:='0';
                        Spulse<='1';                           
                    elsif(pre_state = cur_state)  then
                        Spulse<='0';                          
                    else
                      temp_err := '1';
                    end if;
                    pre_state := cur_state;   
                end if;
            end if;                                                                
			updown<=Vupdown;
            error <= temp_err;                        
        end process gal16_proc;

count_proc: process(reset,clockh,Spulse)
variable vpulse: std_logic;
begin
if( reset = '0') then 
    --pulse<='0';
	vpulse:='0';
else
    if(rising_edge(clockh)) then
       if vpulse='1' then
           vpulse:='0';
       else vpulse:=Spulse;
       end if;
    end if;

end if;
    pulse<=vpulse;
end process count_proc;
end gal16_arch;