📄 prev_cmp_lab4.qmsg
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lab4 -c lab4 " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off lab4 -c lab4" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "128 " "Info: Allocated 128 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 13:18:01 2009 " "Info: Processing ended: Mon May 11 13:18:01 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 11 13:18:02 2009 " "Info: Processing started: Mon May 11 13:18:02 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off lab4 -c lab4 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lab4 -c lab4 --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 6 -1 0 } } { "g:/quartus7.20/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/quartus7.20/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register Y1\[0\] register CO~reg0 233.43 MHz 4.284 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 233.43 MHz between source register \"Y1\[0\]\" and destination register \"CO~reg0\" (period= 4.284 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.023 ns + Longest register register " "Info: + Longest register to register delay is 4.023 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Y1\[0\] 1 REG LC_X22_Y11_N0 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y11_N0; Fanout = 9; REG Node = 'Y1\[0\]'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1[0] } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.834 ns) + CELL(0.590 ns) 1.424 ns LessThan0~56 2 COMB LC_X22_Y11_N9 8 " "Info: 2: + IC(0.834 ns) + CELL(0.590 ns) = 1.424 ns; Loc. = LC_X22_Y11_N9; Fanout = 8; COMB Node = 'LessThan0~56'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "1.424 ns" { Y1[0] LessThan0~56 } "NODE_NAME" } } { "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.493 ns) + CELL(0.292 ns) 2.209 ns Y1~1004 3 COMB LC_X22_Y11_N5 3 " "Info: 3: + IC(0.493 ns) + CELL(0.292 ns) = 2.209 ns; Loc. = LC_X22_Y11_N5; Fanout = 3; COMB Node = 'Y1~1004'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.785 ns" { LessThan0~56 Y1~1004 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.442 ns) 3.078 ns LessThan1~77 4 COMB LC_X22_Y11_N2 2 " "Info: 4: + IC(0.427 ns) + CELL(0.442 ns) = 3.078 ns; Loc. = LC_X22_Y11_N2; Fanout = 2; COMB Node = 'LessThan1~77'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.869 ns" { Y1~1004 LessThan1~77 } "NODE_NAME" } } { "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.478 ns) 4.023 ns CO~reg0 5 REG LC_X22_Y11_N6 1 " "Info: 5: + IC(0.467 ns) + CELL(0.478 ns) = 4.023 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.945 ns" { LessThan1~77 CO~reg0 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.802 ns ( 44.79 % ) " "Info: Total cell delay = 1.802 ns ( 44.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.221 ns ( 55.21 % ) " "Info: Total interconnect delay = 2.221 ns ( 55.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "4.023 ns" { Y1[0] LessThan0~56 Y1~1004 LessThan1~77 CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "4.023 ns" { Y1[0] {} LessThan0~56 {} Y1~1004 {} LessThan1~77 {} CO~reg0 {} } { 0.000ns 0.834ns 0.493ns 0.427ns 0.467ns } { 0.000ns 0.590ns 0.292ns 0.442ns 0.478ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.485 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 7.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK 1 CLK PIN_123 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 5; CLK Node = 'CLK'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.299 ns) + CELL(0.711 ns) 7.485 ns CO~reg0 2 REG LC_X22_Y11_N6 1 " "Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "6.010 ns" { CLK CO~reg0 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.21 % ) " "Info: Total cell delay = 2.186 ns ( 29.21 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.299 ns ( 70.79 % ) " "Info: Total interconnect delay = 5.299 ns ( 70.79 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} CO~reg0 {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.485 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK 1 CLK PIN_123 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 5; CLK Node = 'CLK'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.299 ns) + CELL(0.711 ns) 7.485 ns Y1\[0\] 2 REG LC_X22_Y11_N0 9 " "Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X22_Y11_N0; Fanout = 9; REG Node = 'Y1\[0\]'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "6.010 ns" { CLK Y1[0] } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.21 % ) " "Info: Total cell delay = 2.186 ns ( 29.21 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.299 ns ( 70.79 % ) " "Info: Total interconnect delay = 5.299 ns ( 70.79 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK Y1[0] } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} Y1[0] {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} CO~reg0 {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK Y1[0] } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} Y1[0] {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "4.023 ns" { Y1[0] LessThan0~56 Y1~1004 LessThan1~77 CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "4.023 ns" { Y1[0] {} LessThan0~56 {} Y1~1004 {} LessThan1~77 {} CO~reg0 {} } { 0.000ns 0.834ns 0.493ns 0.427ns 0.467ns } { 0.000ns 0.590ns 0.292ns 0.442ns 0.478ns } "" } } { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} CO~reg0 {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK Y1[0] } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} Y1[0] {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "CO~reg0 EN CLK 5.036 ns register " "Info: tsu for register \"CO~reg0\" (data pin = \"EN\", clock pin = \"CLK\") is 5.036 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.484 ns + Longest pin register " "Info: + Longest pin to register delay is 12.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns EN 1 PIN PIN_7 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_7; Fanout = 2; PIN Node = 'EN'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.877 ns) + CELL(0.590 ns) 8.936 ns process0~1 2 COMB LC_X21_Y11_N5 5 " "Info: 2: + IC(6.877 ns) + CELL(0.590 ns) = 8.936 ns; Loc. = LC_X21_Y11_N5; Fanout = 5; COMB Node = 'process0~1'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.467 ns" { EN process0~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(0.590 ns) 10.670 ns Y1~1004 3 COMB LC_X22_Y11_N5 3 " "Info: 3: + IC(1.144 ns) + CELL(0.590 ns) = 10.670 ns; Loc. = LC_X22_Y11_N5; Fanout = 3; COMB Node = 'Y1~1004'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "1.734 ns" { process0~1 Y1~1004 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.442 ns) 11.539 ns LessThan1~77 4 COMB LC_X22_Y11_N2 2 " "Info: 4: + IC(0.427 ns) + CELL(0.442 ns) = 11.539 ns; Loc. = LC_X22_Y11_N2; Fanout = 2; COMB Node = 'LessThan1~77'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.869 ns" { Y1~1004 LessThan1~77 } "NODE_NAME" } } { "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.478 ns) 12.484 ns CO~reg0 5 REG LC_X22_Y11_N6 1 " "Info: 5: + IC(0.467 ns) + CELL(0.478 ns) = 12.484 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.945 ns" { LessThan1~77 CO~reg0 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.569 ns ( 28.59 % ) " "Info: Total cell delay = 3.569 ns ( 28.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.915 ns ( 71.41 % ) " "Info: Total interconnect delay = 8.915 ns ( 71.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "12.484 ns" { EN process0~1 Y1~1004 LessThan1~77 CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "12.484 ns" { EN {} EN~out0 {} process0~1 {} Y1~1004 {} LessThan1~77 {} CO~reg0 {} } { 0.000ns 0.000ns 6.877ns 1.144ns 0.427ns 0.467ns } { 0.000ns 1.469ns 0.590ns 0.590ns 0.442ns 0.478ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.485 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 7.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK 1 CLK PIN_123 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 5; CLK Node = 'CLK'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.299 ns) + CELL(0.711 ns) 7.485 ns CO~reg0 2 REG LC_X22_Y11_N6 1 " "Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "6.010 ns" { CLK CO~reg0 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.21 % ) " "Info: Total cell delay = 2.186 ns ( 29.21 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.299 ns ( 70.79 % ) " "Info: Total interconnect delay = 5.299 ns ( 70.79 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} CO~reg0 {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "12.484 ns" { EN process0~1 Y1~1004 LessThan1~77 CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "12.484 ns" { EN {} EN~out0 {} process0~1 {} Y1~1004 {} LessThan1~77 {} CO~reg0 {} } { 0.000ns 0.000ns 6.877ns 1.144ns 0.427ns 0.467ns } { 0.000ns 1.469ns 0.590ns 0.590ns 0.442ns 0.478ns } "" } } { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} CO~reg0 {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK CO CO~reg0 13.883 ns register " "Info: tco from clock \"CLK\" to destination pin \"CO\" through register \"CO~reg0\" is 13.883 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.485 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 7.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK 1 CLK PIN_123 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 5; CLK Node = 'CLK'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.299 ns) + CELL(0.711 ns) 7.485 ns CO~reg0 2 REG LC_X22_Y11_N6 1 " "Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "6.010 ns" { CLK CO~reg0 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.21 % ) " "Info: Total cell delay = 2.186 ns ( 29.21 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.299 ns ( 70.79 % ) " "Info: Total interconnect delay = 5.299 ns ( 70.79 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} CO~reg0 {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.174 ns + Longest register pin " "Info: + Longest register to pin delay is 6.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CO~reg0 1 REG LC_X22_Y11_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { CO~reg0 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.066 ns) + CELL(2.108 ns) 6.174 ns CO 2 PIN PIN_38 0 " "Info: 2: + IC(4.066 ns) + CELL(2.108 ns) = 6.174 ns; Loc. = PIN_38; Fanout = 0; PIN Node = 'CO'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "6.174 ns" { CO~reg0 CO } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 34.14 % ) " "Info: Total cell delay = 2.108 ns ( 34.14 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.066 ns ( 65.86 % ) " "Info: Total interconnect delay = 4.066 ns ( 65.86 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "6.174 ns" { CO~reg0 CO } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "6.174 ns" { CO~reg0 {} CO {} } { 0.000ns 4.066ns } { 0.000ns 2.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} CO~reg0 {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "6.174 ns" { CO~reg0 CO } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "6.174 ns" { CO~reg0 {} CO {} } { 0.000ns 4.066ns } { 0.000ns 2.108ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "CO~reg0 CLR CLK 3.543 ns register " "Info: th for register \"CO~reg0\" (data pin = \"CLR\", clock pin = \"CLK\") is 3.543 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.485 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 7.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK 1 CLK PIN_123 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 5; CLK Node = 'CLK'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.299 ns) + CELL(0.711 ns) 7.485 ns CO~reg0 2 REG LC_X22_Y11_N6 1 " "Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "6.010 ns" { CLK CO~reg0 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.21 % ) " "Info: Total cell delay = 2.186 ns ( 29.21 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.299 ns ( 70.79 % ) " "Info: Total interconnect delay = 5.299 ns ( 70.79 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} CO~reg0 {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.957 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.957 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLR 1 PIN PIN_10 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 7; PIN Node = 'CLR'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.071 ns) + CELL(0.114 ns) 2.654 ns process0~1 2 COMB LC_X21_Y11_N5 5 " "Info: 2: + IC(1.071 ns) + CELL(0.114 ns) = 2.654 ns; Loc. = LC_X21_Y11_N5; Fanout = 5; COMB Node = 'process0~1'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "1.185 ns" { CLR process0~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(0.607 ns) 3.957 ns CO~reg0 3 REG LC_X22_Y11_N6 1 " "Info: 3: + IC(0.696 ns) + CELL(0.607 ns) = 3.957 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'" { } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { process0~1 CO~reg0 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.190 ns ( 55.34 % ) " "Info: Total cell delay = 2.190 ns ( 55.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.767 ns ( 44.66 % ) " "Info: Total interconnect delay = 1.767 ns ( 44.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "3.957 ns" { CLR process0~1 CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "3.957 ns" { CLR {} CLR~out0 {} process0~1 {} CO~reg0 {} } { 0.000ns 0.000ns 1.071ns 0.696ns } { 0.000ns 1.469ns 0.114ns 0.607ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "7.485 ns" { CLK CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "7.485 ns" { CLK {} CLK~out0 {} CO~reg0 {} } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } "" } } { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "3.957 ns" { CLR process0~1 CO~reg0 } "NODE_NAME" } } { "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/quartus7.20/quartus/bin/Technology_Viewer.qrui" "3.957 ns" { CLR {} CLR~out0 {} process0~1 {} CO~reg0 {} } { 0.000ns 0.000ns 1.071ns 0.696ns } { 0.000ns 1.469ns 0.114ns 0.607ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 13:18:03 2009 " "Info: Processing ended: Mon May 11 13:18:03 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2 s " "Info: Quartus II Full Compilation was successful. 0 errors, 2 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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