prev_cmp_lab4.qmsg

利用FPGA做出十进制加减法！带有进位借位显示

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.557 ns register register " "Info: Estimated most critical path is register to register delay of 3.557 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Y1\[0\] 1 REG LAB_X22_Y11 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X22_Y11; Fanout = 9; REG Node = 'Y1\[0\]'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1[0] } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.292 ns) 0.969 ns Add0~113 2 COMB LAB_X21_Y11 2 " "Info: 2: + IC(0.677 ns) + CELL(0.292 ns) = 0.969 ns; Loc. = LAB_X21_Y11; Fanout = 2; COMB Node = 'Add0~113'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.969 ns" { Y1[0] Add0~113 } "NODE_NAME" } } { "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "g:/quartus7.20/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.442 ns) 1.862 ns Y1~1002 3 COMB LAB_X22_Y11 3 " "Info: 3: + IC(0.451 ns) + CELL(0.442 ns) = 1.862 ns; Loc. = LAB_X22_Y11; Fanout = 3; COMB Node = 'Y1~1002'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { Add0~113 Y1~1002 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.114 ns) 2.755 ns Y1~1006 4 COMB LAB_X21_Y11 1 " "Info: 4: + IC(0.779 ns) + CELL(0.114 ns) = 2.755 ns; Loc. = LAB_X21_Y11; Fanout = 1; COMB Node = 'Y1~1006'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { Y1~1002 Y1~1006 } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.064 ns) + CELL(0.738 ns) 3.557 ns Y1\[1\] 5 REG LAB_X21_Y11 7 " "Info: 5: + IC(0.064 ns) + CELL(0.738 ns) = 3.557 ns; Loc. = LAB_X21_Y11; Fanout = 7; REG Node = 'Y1\[1\]'" {  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "0.802 ns" { Y1~1006 Y1[1] } "NODE_NAME" } } { "lab4.vhd" "" { Text "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.586 ns ( 44.59 % ) " "Info: Total cell delay = 1.586 ns ( 44.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.971 ns ( 55.41 % ) " "Info: Total interconnect delay = 1.971 ns ( 55.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus7.20/quartus/bin/TimingClosureFloorplan.fld" "" "3.557 ns" { Y1[0] Add0~113 Y1~1002 Y1~1006 Y1[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X14_Y0 X27_Y14 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "G:/Quartus7.20/quartus/EDA实验/实验4/lab4.fit.smsg " "Info: Generated suppressed messages file G:/Quartus7.20/quartus/EDA实验/实验4/lab4.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "168 " "Info: Allocated 168 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 13:17:56 2009 " "Info: Processing ended: Mon May 11 13:17:56 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 11 13:17:59 2009 " "Info: Processing started: Mon May 11 13:17:59 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}