lab4.tan.rpt

利用FPGA做出十进制加减法！带有进位借位显示

; N/A   ; None         ; 4.373 ns   ; CTRL ; Y1[2]   ; CLK      ;
; N/A   ; None         ; 4.221 ns   ; CTRL ; Y1[3]   ; CLK      ;
; N/A   ; None         ; 3.339 ns   ; EN   ; Y1[0]   ; CLK      ;
; N/A   ; None         ; 1.388 ns   ; CTRL ; Y1[0]   ; CLK      ;
; N/A   ; None         ; -1.246 ns  ; CLR  ; CO~reg0 ; CLK      ;
; N/A   ; None         ; -1.534 ns  ; CLR  ; Y1[1]   ; CLK      ;
; N/A   ; None         ; -1.548 ns  ; CLR  ; Y1[2]   ; CLK      ;
; N/A   ; None         ; -1.700 ns  ; CLR  ; Y1[3]   ; CLK      ;
; N/A   ; None         ; -2.942 ns  ; CLR  ; Y1[0]   ; CLK      ;
+-------+--------------+------------+------+---------+----------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+---------+------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To   ; From Clock ;
+-------+--------------+------------+---------+------+------------+
; N/A   ; None         ; 13.883 ns  ; CO~reg0 ; CO   ; CLK        ;
; N/A   ; None         ; 11.751 ns  ; Y1[0]   ; Y[0] ; CLK        ;
; N/A   ; None         ; 11.694 ns  ; Y1[3]   ; Y[3] ; CLK        ;
; N/A   ; None         ; 11.693 ns  ; Y1[2]   ; Y[2] ; CLK        ;
; N/A   ; None         ; 11.564 ns  ; Y1[1]   ; Y[1] ; CLK        ;
+-------+--------------+------------+---------+------+------------+


+---------------------------------------------------------------------+
; th                                                                  ;
+---------------+-------------+-----------+------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To      ; To Clock ;
+---------------+-------------+-----------+------+---------+----------+
; N/A           ; None        ; 3.543 ns  ; CLR  ; CO~reg0 ; CLK      ;
; N/A           ; None        ; 3.513 ns  ; CLR  ; Y1[1]   ; CLK      ;
; N/A           ; None        ; 2.994 ns  ; CLR  ; Y1[0]   ; CLK      ;
; N/A           ; None        ; 2.820 ns  ; CLR  ; Y1[3]   ; CLK      ;
; N/A           ; None        ; 2.820 ns  ; CLR  ; Y1[2]   ; CLK      ;
; N/A           ; None        ; -1.243 ns ; CTRL ; Y1[2]   ; CLK      ;
; N/A           ; None        ; -1.261 ns ; CTRL ; Y1[1]   ; CLK      ;
; N/A           ; None        ; -1.336 ns ; CTRL ; Y1[0]   ; CLK      ;
; N/A           ; None        ; -1.449 ns ; CTRL ; Y1[3]   ; CLK      ;
; N/A           ; None        ; -2.378 ns ; CTRL ; CO~reg0 ; CLK      ;
; N/A           ; None        ; -2.739 ns ; EN   ; CO~reg0 ; CLK      ;
; N/A           ; None        ; -2.768 ns ; EN   ; Y1[1]   ; CLK      ;
; N/A           ; None        ; -3.287 ns ; EN   ; Y1[0]   ; CLK      ;
; N/A           ; None        ; -3.461 ns ; EN   ; Y1[3]   ; CLK      ;
; N/A           ; None        ; -3.461 ns ; EN   ; Y1[2]   ; CLK      ;
+---------------+-------------+-----------+------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon May 11 13:18:02 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lab4 -c lab4 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 233.43 MHz between source register "Y1[0]" and destination register "CO~reg0" (period= 4.284 ns)
    Info: + Longest register to register delay is 4.023 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y11_N0; Fanout = 9; REG Node = 'Y1[0]'
        Info: 2: + IC(0.834 ns) + CELL(0.590 ns) = 1.424 ns; Loc. = LC_X22_Y11_N9; Fanout = 8; COMB Node = 'LessThan0~56'
        Info: 3: + IC(0.493 ns) + CELL(0.292 ns) = 2.209 ns; Loc. = LC_X22_Y11_N5; Fanout = 3; COMB Node = 'Y1~1004'
        Info: 4: + IC(0.427 ns) + CELL(0.442 ns) = 3.078 ns; Loc. = LC_X22_Y11_N2; Fanout = 2; COMB Node = 'LessThan1~77'
        Info: 5: + IC(0.467 ns) + CELL(0.478 ns) = 4.023 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'
        Info: Total cell delay = 1.802 ns ( 44.79 % )
        Info: Total interconnect delay = 2.221 ns ( 55.21 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 7.485 ns
            Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 5; CLK Node = 'CLK'
            Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'
            Info: Total cell delay = 2.186 ns ( 29.21 % )
            Info: Total interconnect delay = 5.299 ns ( 70.79 % )
        Info: - Longest clock path from clock "CLK" to source register is 7.485 ns
            Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 5; CLK Node = 'CLK'
            Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X22_Y11_N0; Fanout = 9; REG Node = 'Y1[0]'
            Info: Total cell delay = 2.186 ns ( 29.21 % )
            Info: Total interconnect delay = 5.299 ns ( 70.79 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "CO~reg0" (data pin = "EN", clock pin = "CLK") is 5.036 ns
    Info: + Longest pin to register delay is 12.484 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_7; Fanout = 2; PIN Node = 'EN'
        Info: 2: + IC(6.877 ns) + CELL(0.590 ns) = 8.936 ns; Loc. = LC_X21_Y11_N5; Fanout = 5; COMB Node = 'process0~1'
        Info: 3: + IC(1.144 ns) + CELL(0.590 ns) = 10.670 ns; Loc. = LC_X22_Y11_N5; Fanout = 3; COMB Node = 'Y1~1004'
        Info: 4: + IC(0.427 ns) + CELL(0.442 ns) = 11.539 ns; Loc. = LC_X22_Y11_N2; Fanout = 2; COMB Node = 'LessThan1~77'
        Info: 5: + IC(0.467 ns) + CELL(0.478 ns) = 12.484 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'
        Info: Total cell delay = 3.569 ns ( 28.59 % )
        Info: Total interconnect delay = 8.915 ns ( 71.41 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 7.485 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'
        Info: Total cell delay = 2.186 ns ( 29.21 % )
        Info: Total interconnect delay = 5.299 ns ( 70.79 % )
Info: tco from clock "CLK" to destination pin "CO" through register "CO~reg0" is 13.883 ns
    Info: + Longest clock path from clock "CLK" to source register is 7.485 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'
        Info: Total cell delay = 2.186 ns ( 29.21 % )
        Info: Total interconnect delay = 5.299 ns ( 70.79 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.174 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'
        Info: 2: + IC(4.066 ns) + CELL(2.108 ns) = 6.174 ns; Loc. = PIN_38; Fanout = 0; PIN Node = 'CO'
        Info: Total cell delay = 2.108 ns ( 34.14 % )
        Info: Total interconnect delay = 4.066 ns ( 65.86 % )
Info: th for register "CO~reg0" (data pin = "CLR", clock pin = "CLK") is 3.543 ns
    Info: + Longest clock path from clock "CLK" to destination register is 7.485 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'
        Info: Total cell delay = 2.186 ns ( 29.21 % )
        Info: Total interconnect delay = 5.299 ns ( 70.79 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 3.957 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 7; PIN Node = 'CLR'
        Info: 2: + IC(1.071 ns) + CELL(0.114 ns) = 2.654 ns; Loc. = LC_X21_Y11_N5; Fanout = 5; COMB Node = 'process0~1'
        Info: 3: + IC(0.696 ns) + CELL(0.607 ns) = 3.957 ns; Loc. = LC_X22_Y11_N6; Fanout = 1; REG Node = 'CO~reg0'
        Info: Total cell delay = 2.190 ns ( 55.34 % )
        Info: Total interconnect delay = 1.767 ns ( 44.66 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 109 megabytes of memory during processing
    Info: Processing ended: Mon May 11 13:18:03 2009
    Info: Elapsed time: 00:00:01