📄 cnt65536.rpt
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 43 C SOFT t 0 0 0 0 6 1 0 |LPM_ADD_SUB:235|addcore:adder|addcore:adder0|result_node5
(32) 48 C SOFT t 0 0 0 0 7 1 0 |LPM_ADD_SUB:235|addcore:adder|addcore:adder0|result_node6
- 34 C SOFT t 0 0 0 0 8 1 0 |LPM_ADD_SUB:235|addcore:adder|addcore:adder0|result_node7
- 54 D SOFT t 0 0 0 0 14 1 0 |LPM_ADD_SUB:235|addcore:adder|addcore:adder1|result_node5
- 60 D SOFT t 0 0 0 0 15 1 0 |LPM_ADD_SUB:235|addcore:adder|addcore:adder1|result_node6
- 63 D SOFT t 0 0 0 0 16 1 0 |LPM_ADD_SUB:235|addcore:adder|addcore:adder1|result_node7
- 39 C SOFT t 0 0 0 0 2 1 0 |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|gcp2
- 38 C SOFT t 0 0 0 0 6 1 0 |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|result_node5
- 44 C SOFT t 0 0 0 0 7 1 0 |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|result_node6
- 42 C SOFT t 0 0 0 0 8 1 0 |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|result_node7
- 50 D SOFT t 0 0 0 0 14 1 0 |LPM_ADD_SUB:316|addcore:adder|addcore:adder1|result_node5
- 61 D SOFT t 0 0 0 0 15 1 0 |LPM_ADD_SUB:316|addcore:adder|addcore:adder1|result_node6
- 59 D SOFT t 0 0 0 0 16 1 0 |LPM_ADD_SUB:316|addcore:adder|addcore:adder1|result_node7
- 55 D SOFT s t 0 0 0 1 16 1 0 ~659~1
(38) 56 D SOFT s t 0 0 0 1 16 1 0 ~662~1
- 58 D SOFT s t 0 0 0 1 16 1 0 ~664~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: e:\vhdl\4-7\cnt65536.rpt
cnt65536
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----- LC21 CQ0
| +--- LC17 CQ7
| | +- LC20 CQ15
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'B'
LC | | | | A B C D | Logic cells that feed LAB 'B':
LC17 -> - * - | - * * * | <-- CQ7
LC20 -> - - * | - * - * | <-- CQ15
Pin
43 -> - - - | - - - - | <-- CLK
12 -> * * * | - * * * | <-- EN
11 -> * * * | - * * * | <-- RST
9 -> - * * | - * * * | <-- U_D
LC34 -> - * - | - * - - | <-- |LPM_ADD_SUB:235|addcore:adder|addcore:adder0|result_node7
LC63 -> - - * | - * - - | <-- |LPM_ADD_SUB:235|addcore:adder|addcore:adder1|result_node7
LC42 -> - * - | - * - - | <-- |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|result_node7
LC59 -> - - * | - * - - | <-- |LPM_ADD_SUB:316|addcore:adder|addcore:adder1|result_node7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdl\4-7\cnt65536.rpt
cnt65536
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------------------- LC41 CQ1
| +------------------------- LC40 CQ2
| | +----------------------- LC37 CQ3
| | | +--------------------- LC36 CQ4
| | | | +------------------- LC35 CQ5
| | | | | +----------------- LC33 CQ6
| | | | | | +--------------- LC46 CQ8
| | | | | | | +------------- LC43 |LPM_ADD_SUB:235|addcore:adder|addcore:adder0|result_node5
| | | | | | | | +----------- LC48 |LPM_ADD_SUB:235|addcore:adder|addcore:adder0|result_node6
| | | | | | | | | +--------- LC34 |LPM_ADD_SUB:235|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | | +------- LC39 |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|gcp2
| | | | | | | | | | | +----- LC38 |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | | | | +--- LC44 |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|result_node6
| | | | | | | | | | | | | +- LC42 |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC41 -> * * * * - - * * * * * * * * | - - * * | <-- CQ1
LC40 -> - * * * - - * * * * * * * * | - - * * | <-- CQ2
LC37 -> - - * * - - * * * * - * * * | - - * * | <-- CQ3
LC36 -> - - - * - - * * * * - * * * | - - * * | <-- CQ4
LC35 -> - - - - * - * * * * - * * * | - - * * | <-- CQ5
LC33 -> - - - - - * * - * * - - * * | - - * * | <-- CQ6
LC43 -> - - - - * - - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:235|addcore:adder|addcore:adder0|result_node5
LC48 -> - - - - - * - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:235|addcore:adder|addcore:adder0|result_node6
LC39 -> - - * - - - - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|gcp2
LC38 -> - - - - * - - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|result_node5
LC44 -> - - - - - * - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:316|addcore:adder|addcore:adder0|result_node6
Pin
43 -> - - - - - - - - - - - - - - | - - - - | <-- CLK
12 -> * * * * * * * - - - - - - - | - * * * | <-- EN
11 -> * * * * * * * - - - - - - - | - * * * | <-- RST
9 -> * * * * * * * - - - - - - - | - * * * | <-- U_D
LC21 -> * * * * - - * * * * - * * * | - - * * | <-- CQ0
LC17 -> - - - - - - * - - * - - - * | - * * * | <-- CQ7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdl\4-7\cnt65536.rpt
cnt65536
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC53 COUT
| +----------------------------- LC57 CQ9
| | +--------------------------- LC51 CQ10
| | | +------------------------- LC49 CQ11
| | | | +----------------------- LC52 CQ12
| | | | | +--------------------- LC62 CQ13
| | | | | | +------------------- LC64 CQ14
| | | | | | | +----------------- LC54 |LPM_ADD_SUB:235|addcore:adder|addcore:adder1|result_node5
| | | | | | | | +--------------- LC60 |LPM_ADD_SUB:235|addcore:adder|addcore:adder1|result_node6
| | | | | | | | | +------------- LC63 |LPM_ADD_SUB:235|addcore:adder|addcore:adder1|result_node7
| | | | | | | | | | +----------- LC50 |LPM_ADD_SUB:316|addcore:adder|addcore:adder1|result_node5
| | | | | | | | | | | +--------- LC61 |LPM_ADD_SUB:316|addcore:adder|addcore:adder1|result_node6
| | | | | | | | | | | | +------- LC59 |LPM_ADD_SUB:316|addcore:adder|addcore:adder1|result_node7
| | | | | | | | | | | | | +----- LC55 ~659~1
| | | | | | | | | | | | | | +--- LC56 ~662~1
| | | | | | | | | | | | | | | +- LC58 ~664~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC57 -> * * * * * - - * * * * * * * * * | - - - * | <-- CQ9
LC51 -> * - * * * - - * * * * * * * * * | - - - * | <-- CQ10
LC49 -> * - - * * - - * * * * * * * * * | - - - * | <-- CQ11
LC52 -> * - - - * - - * * * * * * * * * | - - - * | <-- CQ12
LC62 -> * - - - - * - * * * * * * * * * | - - - * | <-- CQ13
LC64 -> * - - - - - * - * * - * * * * * | - - - * | <-- CQ14
LC54 -> - - - - - * - - - - - - - - - - | - - - * | <-- |LPM_ADD_SUB:235|addcore:adder|addcore:adder1|result_node5
LC60 -> - - - - - - * - - - - - - - - - | - - - * | <-- |LPM_ADD_SUB:235|addcore:adder|addcore:adder1|result_node6
LC50 -> - - - - - * - - - - - - - - - - | - - - * | <-- |LPM_ADD_SUB:316|addcore:adder|addcore:adder1|result_node5
LC61 -> - - - - - - * - - - - - - - - - | - - - * | <-- |LPM_ADD_SUB:316|addcore:adder|addcore:adder1|result_node6
LC55 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~659~1
LC56 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~662~1
LC58 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~664~1
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLK
12 -> - * * * * * * - - - - - - - - - | - * * * | <-- EN
11 -> * * * * * * * - - - - - - - - - | - * * * | <-- RST
9 -> * * * * * * * - - - - - - * * * | - * * * | <-- U_D
LC21 -> * * * * * - - * * * * * * * * * | - - * * | <-- CQ0
LC41 -> * * * * * - - * * * * * * * * * | - - * * | <-- CQ1
LC40 -> * * * * * - - * * * * * * * * * | - - * * | <-- CQ2
LC37 -> * * * * * - - * * * * * * * * * | - - * * | <-- CQ3
LC36 -> * * * * * - - * * * * * * * * * | - - * * | <-- CQ4
LC35 -> * * * * * - - * * * * * * * * * | - - * * | <-- CQ5
LC33 -> * * * * * - - * * * * * * * * * | - - * * | <-- CQ6
LC17 -> * * * * * - - * * * * * * * * * | - * * * | <-- CQ7
LC46 -> * * * * * - - * * * * * * * * * | - - - * | <-- CQ8
LC20 -> * - - - - - - - - * - - * * * * | - * - * | <-- CQ15
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdl\4-7\cnt65536.rpt
cnt65536
** EQUATIONS **
CLK : INPUT;
EN : INPUT;
RST : INPUT;
U_D : INPUT;
-- Node name is 'COUT' = ':21'
-- Equation name is 'COUT', type is output
COUT = DFFE( _EQ001 $ _EQ002, GLOBAL( CLK), VCC, VCC, !RST);
_EQ001 = _LC055 & !_LC056 & !_LC058;
_EQ002 = CQ0 & CQ1 & CQ2 & CQ3 & CQ4 & CQ5 & CQ6 & CQ7 & CQ8 &
CQ9 & CQ10 & CQ11 & CQ12 & CQ13 & CQ14 & CQ15 & U_D;
-- Node name is 'CQ0' = 'CQI0'
-- Equation name is 'CQ0', location is LC021, type is output.
CQ0 = TFFE( EN, GLOBAL( CLK), !RST, VCC, VCC);
-- Node name is 'CQ1' = 'CQI1'
-- Equation name is 'CQ1', location is LC041, type is output.
CQ1 = TFFE( _EQ003, GLOBAL( CLK), !RST, VCC, VCC);
_EQ003 = CQ0 & EN & U_D
# !CQ0 & EN & !U_D;
-- Node name is 'CQ2' = 'CQI2'
-- Equation name is 'CQ2', location is LC040, type is output.
CQ2 = TFFE( _EQ004, GLOBAL( CLK), !RST, VCC, VCC);
_EQ004 = CQ0 & CQ1 & EN & U_D
# !CQ0 & !CQ1 & EN & !U_D;
-- Node name is 'CQ3' = 'CQI3'
-- Equation name is 'CQ3', location is LC037, type is output.
CQ3 = TFFE( _EQ005, GLOBAL( CLK), !RST, VCC, VCC);
_EQ005 = CQ0 & CQ1 & CQ2 & EN & U_D
# !CQ0 & EN & !_LC039 & !U_D;
-- Node name is 'CQ4' = 'CQI4'
-- Equation name is 'CQ4', location is LC036, type is output.
CQ4 = TFFE( _EQ006, GLOBAL( CLK), !RST, VCC, VCC);
_EQ006 = CQ0 & CQ1 & CQ2 & CQ3 & EN & U_D
# !CQ0 & !CQ1 & !CQ2 & !CQ3 & EN & !U_D;
-- Node name is 'CQ5' = 'CQI5'
-- Equation name is 'CQ5', location is LC035, type is output.
CQ5 = DFFE( _EQ007 $ GND, GLOBAL( CLK), !RST, VCC, VCC);
_EQ007 = EN & _LC043 & U_D
# EN & _LC038 & !U_D
# CQ5 & !EN;
-- Node name is 'CQ6' = 'CQI6'
-- Equation name is 'CQ6', location is LC033, type is output.
CQ6 = DFFE( _EQ008 $ GND, GLOBAL( CLK), !RST, VCC, VCC);
_EQ008 = EN & _LC048 & U_D
# EN & _LC044 & !U_D
# CQ6 & !EN;
-- Node name is 'CQ7' = 'CQI7'
-- Equation name is 'CQ7', location is LC017, type is output.
CQ7 = DFFE( _EQ009 $ GND, GLOBAL( CLK), !RST, VCC, VCC);
_EQ009 = EN & _LC034 & U_D
# EN & _LC042 & !U_D
# CQ7 & !EN;
-- Node name is 'CQ8' = 'CQI8'
-- Equation name is 'CQ8', location is LC046, type is output.
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