encoder.tan.rpt

来自「编码器信号处理 经过倍频器进行四倍频 后 同时完成鉴相 计数」· RPT 代码 · 共 290 行 · 第 1/5 页

; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; Off                ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Minimum tpd to report                                 ; 0 ns               ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                  ; To                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|8 ; lpm_counter:db_rtl_0|p8count:p8c[0]|2 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|7 ; lpm_counter:db_rtl_0|p8count:p8c[0]|2 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|6 ; lpm_counter:db_rtl_0|p8count:p8c[0]|2 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|5 ; lpm_counter:db_rtl_0|p8count:p8c[0]|2 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|4 ; lpm_counter:db_rtl_0|p8count:p8c[0]|2 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|3 ; lpm_counter:db_rtl_0|p8count:p8c[0]|2 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|2 ; lpm_counter:db_rtl_0|p8count:p8c[0]|2 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|8 ; lpm_counter:db_rtl_0|p8count:p8c[0]|1 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|7 ; lpm_counter:db_rtl_0|p8count:p8c[0]|1 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|6 ; lpm_counter:db_rtl_0|p8count:p8c[0]|1 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|5 ; lpm_counter:db_rtl_0|p8count:p8c[0]|1 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|4 ; lpm_counter:db_rtl_0|p8count:p8c[0]|1 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|3 ; lpm_counter:db_rtl_0|p8count:p8c[0]|1 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|2 ; lpm_counter:db_rtl_0|p8count:p8c[0]|1 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|1 ; lpm_counter:db_rtl_0|p8count:p8c[0]|1 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|8 ; lpm_counter:db_rtl_0|p8count:p8c[1]|8 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|7 ; lpm_counter:db_rtl_0|p8count:p8c[1]|8 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|6 ; lpm_counter:db_rtl_0|p8count:p8c[1]|8 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|5 ; lpm_counter:db_rtl_0|p8count:p8c[1]|8 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|4 ; lpm_counter:db_rtl_0|p8count:p8c[1]|8 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|3 ; lpm_counter:db_rtl_0|p8count:p8c[1]|8 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|2 ; lpm_counter:db_rtl_0|p8count:p8c[1]|8 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[0]|1 ; lpm_counter:db_rtl_0|p8count:p8c[1]|8 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 43.48 MHz ( period = 23.000 ns )                    ; lpm_counter:db_rtl_0|p8count:p8c[1]|8 ; lpm_counter:db_rtl_0|p8count:p8c[1]|8 ; clk        ; clk      ; None                        ; None                      ; 18.000 ns               ;