vhdl减法.txt

来自「实现乘法功能」· 文本 代码 · 共 18 行

entity lcnt is 
port(clk:in std_logic; 
q:out std_logic); 
end lcnt; 
architecture art of lcnt is 
signal count:std_logic(4 downto 0); 
begin 
process(clk) 
begin 
if clk'event and clk='1' then 
if count='0' then 
count<=24; 
else count<=count-1; 
end if; 
end if 
end process; 
end art;