module dtrdt_v.txt

实现乘法功能

module dtrdt_v;

	// Inputs
	reg CLK;
	reg EN;

	// Outputs
	wire [3:0] LAMPA;
	wire [3:0] LAMPB;
	wire [7:0] ACOUNT;
	wire [7:0] BCOUNT;

	// Instantiate the Unit Under Test (UUT)
	traffic uut (
		.CLK(CLK), 
		.EN(EN), 
		.LAMPA(LAMPA), 
		.LAMPB(LAMPB), 
		.ACOUNT(ACOUNT), 
		.BCOUNT(BCOUNT)
	);
	 always #10 CLK=~CLK;
	initial begin
		// Initialize Inputs
		CLK = 0;
		EN = 0;

		// Wait 100 ns for global reset to finish
		#100 EN=1;
        
		// Add stimulus here

	end
      
endmodule