code.v

2dpsk,maxplus软件,包含连接原理图各个模块程序代码,可运行,管脚已经封装,可直接下载到FPGA芯片

//差分编码

module code(clk,m,out);
input clk;
input m;
output out;

reg a;
reg out;
wire b;
assign b=a^m;

always @(posedge clk)
begin
a=m;
out=b;
end

endmodule