div32.v

来自「2dpsk,maxplus软件,包含连接原理图各个模块程序代码,可运行,管脚已经」· Verilog 代码 · 共 22 行

module div32(
clk,
divout);

input clk;
output divout;

reg [4:0]div;
reg divout;

initial
div=0;

always @(posedge clk)
begin
div=div+1;
divout=div[4];
end

endmodule