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📄 2psk_tiaozhi.rpt

📁 2dpsk,maxplus软件,包含连接原理图各个模块程序代码,可运行,管脚已经封装,可直接下载到FPGA芯片
💻 RPT
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-- Node name is '|f2_zb:6|:28' 
-- Equation name is '_LC7_C11', type is buried 
_LC7_C11 = DFFE( _EC12_C,  _LC1_D3,  VCC,  VCC,  VCC);

-- Node name is '|f2_zb:6|:29' 
-- Equation name is '_LC4_C11', type is buried 
_LC4_C11 = DFFE( _EC4_C,  _LC1_D3,  VCC,  VCC,  VCC);

-- Node name is '|f2_zb:6|:30' 
-- Equation name is '_LC6_C10', type is buried 
_LC6_C10 = DFFE( _EC16_C,  _LC1_D3,  VCC,  VCC,  VCC);

-- Node name is '|f2_zb:6|:31' 
-- Equation name is '_LC4_C10', type is buried 
_LC4_C10 = DFFE( _EC2_C,  _LC1_D3,  VCC,  VCC,  VCC);

-- Node name is '|f2_zb:6|:32' 
-- Equation name is '_LC2_C8', type is buried 
_LC2_C8  = DFFE( _EC11_C,  _LC1_D3,  VCC,  VCC,  VCC);

-- Node name is '|f2_zb:6|:33' 
-- Equation name is '_LC8_C7', type is buried 
_LC8_C7  = DFFE( _EC1_C,  _LC1_D3,  VCC,  VCC,  VCC);

-- Node name is '|mux:1|:54' 
-- Equation name is '_LC2_C16', type is buried 
_LC2_C16 = LCELL( _EQ026);
  _EQ026 =  _LC1_C7 &  _LC5_C16
         # !_LC1_C7 &  _LC6_C16;

-- Node name is '|mux:1|:55' 
-- Equation name is '_LC4_C16', type is buried 
_LC4_C16 = LCELL( _EQ027);
  _EQ027 =  _LC1_C7 &  _LC1_C16
         # !_LC1_C7 &  _LC3_C16;

-- Node name is '|mux:1|:56' 
-- Equation name is '_LC3_C11', type is buried 
_LC3_C11 = LCELL( _EQ028);
  _EQ028 =  _LC1_C7 &  _LC6_C11
         # !_LC1_C7 &  _LC7_C11;

-- Node name is '|mux:1|:57' 
-- Equation name is '_LC5_C11', type is buried 
_LC5_C11 = LCELL( _EQ029);
  _EQ029 =  _LC1_C7 &  _LC2_C11
         # !_LC1_C7 &  _LC4_C11;

-- Node name is '|mux:1|:58' 
-- Equation name is '_LC2_C10', type is buried 
_LC2_C10 = LCELL( _EQ030);
  _EQ030 =  _LC1_C7 &  _LC5_C10
         # !_LC1_C7 &  _LC6_C10;

-- Node name is '|mux:1|:59' 
-- Equation name is '_LC1_C10', type is buried 
_LC1_C10 = LCELL( _EQ031);
  _EQ031 =  _LC1_C7 &  _LC3_C10
         # !_LC1_C7 &  _LC4_C10;

-- Node name is '|mux:1|:60' 
-- Equation name is '_LC8_C8', type is buried 
_LC8_C8  = LCELL( _EQ032);
  _EQ032 =  _LC1_C7 &  _LC1_C8
         # !_LC1_C7 &  _LC2_C8;

-- Node name is '|mux:1|:61' 
-- Equation name is '_LC5_C7', type is buried 
_LC5_C7  = LCELL( _EQ033);
  _EQ033 =  _LC1_C7 &  _LC7_C7
         # !_LC1_C7 &  _LC8_C7;

-- Node name is '|m5:13|:40' = '|m5:13|cnt0' 
-- Equation name is '_LC6_C12', type is buried 
_LC6_C12 = DFFE( _EQ034,  _LC2_C6,  VCC,  VCC,  VCC);
  _EQ034 =  _LC8_C12
         #  _LC1_C12 & !_LC6_C12 & !_LC7_C12;

-- Node name is '|m5:13|:39' = '|m5:13|cnt1' 
-- Equation name is '_LC8_C12', type is buried 
_LC8_C12 = DFFE( _EQ035,  _LC2_C6,  VCC,  VCC,  VCC);
  _EQ035 =  _LC1_C12 & !_LC6_C12 & !_LC8_C12
         #  _LC7_C12;

-- Node name is '|m5:13|:38' = '|m5:13|cnt2' 
-- Equation name is '_LC7_C12', type is buried 
_LC7_C12 = DFFE( _EQ036,  _LC2_C6,  VCC,  VCC,  VCC);
  _EQ036 =  _LC2_C12 & !_LC6_C12 & !_LC8_C12
         #  _LC5_C12;

-- Node name is '|m5:13|:37' = '|m5:13|cnt3' 
-- Equation name is '_LC5_C12', type is buried 
_LC5_C12 = DFFE( _EQ037,  _LC2_C6,  VCC,  VCC,  VCC);
  _EQ037 =  _LC2_C12 & !_LC6_C12 & !_LC8_C12
         #  _LC3_C12;

-- Node name is '|m5:13|:36' = '|m5:13|cnt4' 
-- Equation name is '_LC3_C12', type is buried 
_LC3_C12 = DFFE( _EQ038,  _LC2_C6,  VCC,  VCC,  VCC);
  _EQ038 = !_LC6_C12 &  _LC7_C12
         #  _LC6_C12 & !_LC7_C12
         #  _LC2_C12 & !_LC6_C12 & !_LC8_C12;

-- Node name is '|m5:13|~3~1' 
-- Equation name is '_LC1_C12', type is buried 
-- synthesized logic cell 
_LC1_C12 = LCELL( _EQ039);
  _EQ039 = !_LC3_C12 & !_LC5_C12;

-- Node name is '|m5:13|~3~2' 
-- Equation name is '_LC2_C12', type is buried 
-- synthesized logic cell 
_LC2_C12 = LCELL( _EQ040);
  _EQ040 =  _LC1_C12 & !_LC7_C12;

-- Node name is '|m5:13|:57' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = DFFE( _EQ041,  _LC2_C6,  VCC,  VCC,  VCC);
  _EQ041 =  _LC1_C12 & !_LC6_C12 & !_LC7_C12
         #  _LC8_C12;

-- Node name is '|f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_D', type is memory 
_EC2_D   = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC12_D', type is memory 
_EC12_D  = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_D', type is memory 
_EC1_D   = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC10_D', type is memory 
_EC10_D  = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_D', type is memory 
_EC4_D   = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_D', type is memory 
_EC9_D   = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC3_D', type is memory 
_EC3_D   = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC11_D', type is memory 
_EC11_D  = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, _LC5_D3, _LC2_D3, _LC3_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, _LC4_D3, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_C', type is memory 
_EC1_C   = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC11_C', type is memory 
_EC11_C  = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_C', type is memory 
_EC2_C   = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC16_C', type is memory 
_EC16_C  = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_C', type is memory 
_EC4_C   = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC12_C', type is memory 
_EC12_C  = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC6_C', type is memory 
_EC6_C   = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_C', type is memory 
_EC9_C   = MEMORY_SEGMENT( VCC, _LC1_D3, VCC, GND, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, _LC2_C7, _LC1_C11, _LC3_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, _LC4_C7, VCC, VCC, VCC, VCC, VCC, VCC);



Project Information                             f:\2psk_final\2psk_tiaozhi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,355K

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