📄 2psk_tiaozhi.rpt
字号:
D15 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
C37 8/16( 50%) 0/16( 0%) 8/16( 50%) 1/2 2/6 5/88( 5%)
D37 8/16( 50%) 8/16( 50%) 0/16( 0%) 1/2 2/6 5/88( 5%)
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 11/96 ( 11%)
Total logic cells used: 62/1728 ( 3%)
Total embedded cells used: 16/96 ( 16%)
Total EABs used: 2/6 ( 33%)
Average fan-in: 2.40/4 ( 60%)
Total fan-in: 149/6912 ( 2%)
Total input pins required: 1
Total input I/O cell registers required: 0
Total output pins required: 11
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 62
Total flipflops required: 49
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 2/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 5 0 8 8 3 0 6 7 8 0 0 0 6 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51/8
D: 0 0 7 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11/8
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 7 5 0 8 8 3 0 6 7 8 0 0 4 6 0 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62/16
Device-Specific Information: f:\2psk_final\2psk_tiaozhi.rpt
2psk_tiaozhi
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G ^ 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\2psk_final\2psk_tiaozhi.rpt
2psk_tiaozhi
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
14 - - C -- OUTPUT 0 1 0 0 m
12 - - C -- OUTPUT 0 1 0 0 m_clk
11 - - C -- OUTPUT 0 1 0 0 m_code
68 - - - 07 OUTPUT 0 1 0 0 2psk0
67 - - - 08 OUTPUT 0 1 0 0 2psk1
65 - - - 09 OUTPUT 0 1 0 0 2psk2
64 - - - 10 OUTPUT 0 1 0 0 2psk3
63 - - - 11 OUTPUT 0 1 0 0 2psk4
62 - - - 12 OUTPUT 0 1 0 0 2psk5
60 - - - 15 OUTPUT 0 1 0 0 2psk6
59 - - - 16 OUTPUT 0 1 0 0 2psk7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\2psk_final\2psk_tiaozhi.rpt
2psk_tiaozhi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 07 DFFE 0 2 0 1 |code:2|a (|code:2|:5)
- 1 - C 07 DFFE 0 3 1 8 |code:2|:9
- 1 - D 15 AND2 0 3 0 3 |div64:4|lpm_add_sub:23|addcore:adder|:67
- 1 - D 03 DFFE + 0 3 0 40 |div64:4|div5 (|div64:4|:9)
- 7 - D 03 DFFE + 0 2 0 1 |div64:4|div4 (|div64:4|:10)
- 6 - D 03 DFFE + 0 1 0 2 |div64:4|div3 (|div64:4|:11)
- 4 - D 15 DFFE + 0 2 0 1 |div64:4|div2 (|div64:4|:12)
- 2 - D 15 DFFE + 0 1 0 2 |div64:4|div1 (|div64:4|:13)
- 3 - D 15 DFFE + 0 0 0 3 |div64:4|div0 (|div64:4|:14)
- 2 - C 04 AND2 0 4 0 4 |div1024:3|lpm_add_sub:35|addcore:adder|:87
- 5 - C 06 AND2 0 4 0 4 |div1024:3|lpm_add_sub:35|addcore:adder|:99
- 8 - C 06 DFFE + 0 3 0 1 |div1024:3|div9 (|div1024:3|:13)
- 7 - C 06 DFFE + 0 2 0 2 |div1024:3|div8 (|div1024:3|:14)
- 6 - C 06 DFFE + 0 1 0 3 |div1024:3|div7 (|div1024:3|:15)
- 4 - C 06 DFFE + 0 3 0 1 |div1024:3|div6 (|div1024:3|:16)
- 3 - C 06 DFFE + 0 2 0 2 |div1024:3|div5 (|div1024:3|:17)
- 1 - C 06 DFFE + 0 1 0 3 |div1024:3|div4 (|div1024:3|:18)
- 5 - C 04 DFFE + 0 3 0 1 |div1024:3|div3 (|div1024:3|:19)
- 4 - C 04 DFFE + 0 2 0 2 |div1024:3|div2 (|div1024:3|:20)
- 1 - C 04 DFFE + 0 1 0 3 |div1024:3|div1 (|div1024:3|:21)
- 3 - C 04 DFFE + 0 0 0 4 |div1024:3|div0 (|div1024:3|:22)
- 2 - C 06 DFFE + 0 4 1 8 |div1024:3|:34
- - 2 D -- MEM_SGMT 0 5 0 1 |f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 12 D -- MEM_SGMT 0 5 0 1 |f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 1 D -- MEM_SGMT 0 5 0 1 |f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 10 D -- MEM_SGMT 0 5 0 1 |f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 4 D -- MEM_SGMT 0 5 0 1 |f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 9 D -- MEM_SGMT 0 5 0 1 |f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 3 D -- MEM_SGMT 0 5 0 1 |f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 11 D -- MEM_SGMT 0 5 0 1 |f1_zb:5|rom16_1:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- 4 - D 03 DFFE 0 4 0 8 |f1_zb:5|count3 (|f1_zb:5|:14)
- 3 - D 03 DFFE 0 3 0 9 |f1_zb:5|count2 (|f1_zb:5|:15)
- 2 - D 03 DFFE 0 2 0 10 |f1_zb:5|count1 (|f1_zb:5|:16)
- 5 - D 03 DFFE 0 1 0 11 |f1_zb:5|count0 (|f1_zb:5|:17)
- 5 - C 16 DFFE 0 2 0 1 |f1_zb:5|:26
- 1 - C 16 DFFE 0 2 0 1 |f1_zb:5|:27
- 6 - C 11 DFFE 0 2 0 1 |f1_zb:5|:28
- 2 - C 11 DFFE 0 2 0 1 |f1_zb:5|:29
- 5 - C 10 DFFE 0 2 0 1 |f1_zb:5|:30
- 3 - C 10 DFFE 0 2 0 1 |f1_zb:5|:31
- 1 - C 08 DFFE 0 2 0 1 |f1_zb:5|:32
- 7 - C 07 DFFE 0 2 0 1 |f1_zb:5|:33
- - 1 C -- MEM_SGMT 0 5 0 1 |f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 11 C -- MEM_SGMT 0 5 0 1 |f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 2 C -- MEM_SGMT 0 5 0 1 |f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 16 C -- MEM_SGMT 0 5 0 1 |f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 4 C -- MEM_SGMT 0 5 0 1 |f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 12 C -- MEM_SGMT 0 5 0 1 |f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 6 C -- MEM_SGMT 0 5 0 1 |f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 9 C -- MEM_SGMT 0 5 0 1 |f2_zb:6|rom16_2:U1|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- 4 - C 07 DFFE 0 4 0 8 |f2_zb:6|count3 (|f2_zb:6|:14)
- 3 - C 07 DFFE 0 3 0 9 |f2_zb:6|count2 (|f2_zb:6|:15)
- 1 - C 11 DFFE 0 2 0 10 |f2_zb:6|count1 (|f2_zb:6|:16)
- 2 - C 07 DFFE 0 1 0 11 |f2_zb:6|count0 (|f2_zb:6|:17)
- 6 - C 16 DFFE 0 2 0 1 |f2_zb:6|:26
- 3 - C 16 DFFE 0 2 0 1 |f2_zb:6|:27
- 7 - C 11 DFFE 0 2 0 1 |f2_zb:6|:28
- 4 - C 11 DFFE 0 2 0 1 |f2_zb:6|:29
- 6 - C 10 DFFE 0 2 0 1 |f2_zb:6|:30
- 4 - C 10 DFFE 0 2 0 1 |f2_zb:6|:31
- 2 - C 08 DFFE 0 2 0 1 |f2_zb:6|:32
- 8 - C 07 DFFE 0 2 0 1 |f2_zb:6|:33
- 2 - C 16 OR2 0 3 1 0 |mux:1|:54
- 4 - C 16 OR2 0 3 1 0 |mux:1|:55
- 3 - C 11 OR2 0 3 1 0 |mux:1|:56
- 5 - C 11 OR2 0 3 1 0 |mux:1|:57
- 2 - C 10 OR2 0 3 1 0 |mux:1|:58
- 1 - C 10 OR2 0 3 1 0 |mux:1|:59
- 8 - C 08 OR2 0 3 1 0 |mux:1|:60
- 5 - C 07 OR2 0 3 1 0 |mux:1|:61
- 1 - C 12 AND2 s 0 2 0 4 |m5:13|~3~1
- 2 - C 12 AND2 s 0 2 0 3 |m5:13|~3~2
- 3 - C 12 DFFE 0 5 0 2 |m5:13|cnt4 (|m5:13|:36)
- 5 - C 12 DFFE 0 5 0 2 |m5:13|cnt3 (|m5:13|:37)
- 7 - C 12 DFFE 0 5 0 5 |m5:13|cnt2 (|m5:13|:38)
- 8 - C 12 DFFE 0 4 0 5 |m5:13|cnt1 (|m5:13|:39)
- 6 - C 12 DFFE 0 4 0 5 |m5:13|cnt0 (|m5:13|:40)
- 4 - C 12 DFFE 0 5 1 2 |m5:13|:57
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\2psk_final\2psk_tiaozhi.rpt
2psk_tiaozhi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 26/144( 18%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 7/144( 4%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 8/24( 33%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\2psk_final\2psk_tiaozhi.rpt
2psk_tiaozhi
** CLOCK SIGNALS **
Type Fan-out Name
DFF 41 |div64:4|div5
INPUT 17 clk
DFF 9 |div1024:3|:34
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