add2.v

来自「自己写一个关于维mesh结构的noc网络」· Verilog 代码 · 共 49 行

module add2();
 reg add_c, reduce_c;
 reg [1:0] count_b;
 reg clk;
 
 always@(add_c, reduce_c)
 begin
 if(add_c && ~reduce_c)
 begin
    count_b[0] <= ~count_b[0];
    count_b[1] <= ~count_b[1] & count_b[0];
 end
 else if(~add_c && reduce_c)
 begin
    count_b[0] <= ~count_b[0];
    count_b[1] <= ~count_b[1] & ~count_b[0];
 end
 else count_b <= count_b;
 
 end
 
 always clk = #5 ~clk;
 initial
 begin
     count_b <= 0;
     clk <= 0;
     add_c <= 0;
     reduce_c <= 0;
     #5;
     add_c <= 1;
     reduce_c <= 0;
     clk <= 1; 
     #5;
     clk <= 0;
     #5;
     add_c <= 1;
     reduce_c <= 1;
     clk <= 1; 
     #5;
     clk <= 0;
     #5;
     add_c <= 0;
     reduce_c <= 1;
     clk <= 1; 
     #5;
     clk <= 0;
 end
endmodule