inctl.v

自己写一个关于维mesh结构的noc网络

/*
This module is a sub-component of mesh_router and is used to control buffer and 
send ack signal to sender.
The control flow of Input Control is described below:
1.	Check whether the req signal from sender is high, if it is?store the data from sender (din) into buffer. Send ack signal to sender go to step 2, else go to step 1.
2.	Check whether the req signal from sender is inactive, if it is go to step 3, else go to step 2.
3.	Check whether the ack signal from receiver is active, if it is go to step 1, else go to step 3.
*/
module inctl(clk, rst, req_in, din, ack_in, ack_out, du_3, dout, req_out, ten);
    input clk, rst, req_in, ack_in, ten;
    input [33:0] din;
    output ack_out, req_out;
    output [33:0] du_3, dout;
    
    parameter WAIT_DATA = 0, WAIT_REQ = 1, TEST = 3;
    parameter PRE_SEND = 0, WAIT_ACK = 1, WAIT_ACK_DOWN = 2;
    reg [1:0] current_state_in;
    reg [1:0] current_state_out;
    reg ackout_v, reqout_v;
    reg [33:0] buffer[1:0];
    reg index_in, index_out;
    reg [1:0] count_b;
    reg add_c, reduce_c;
    
    assign ack_out = ackout_v;
    assign req_out = reqout_v;
    assign dout = (index_out == 0)? buffer[0] : buffer[1];
    assign du_3[33:30] = (index_out == 0)? buffer[0][33:30] : buffer[1][33:30];
    assign du_3[29:27] = 3'b000;
    assign du_3[26:0] = (index_out == 0)? buffer[0][29:3] : buffer[1][29:3];
    
    
    always @(rst, add_c, reduce_c)
    begin
        if(rst == 1)
        begin
            //$display("reset count_b to 0\n");
            count_b <= 0;
        end
        else
        begin            
            if(add_c && ~reduce_c)
            begin
                count_b[0] <= ~count_b[0];
                count_b[1] <= ~count_b[1] & count_b[0];
            end
            if(~add_c && reduce_c)
            begin
                count_b[0] <= ~count_b[0];
                count_b[1] <= ~count_b[1] & ~count_b[0];
            end
           // $display("count_b is %d\n", count_b);
           // $display("the count of used buffer is %d\n", count_b);
        end
    end
    
    always @(posedge clk)//input state machine
    begin
        if(rst == 1)
        begin
            ackout_v <= 0;
            current_state_in <= WAIT_DATA;
            index_in <= 0;
            add_c <= 0;
        end
        else begin
            case(current_state_in)
                WAIT_DATA:
                begin
                     if (ten == 1)
                     begin
                         current_state_in <= TEST;
                     end
                     else  if(req_in == 1)
                       begin
                           if(count_b != 2)
                           begin
                              add_c <= 1;
                              if(index_in == 0) 
                               begin
                                 index_in <= ~index_in;
                                 buffer[0] <= din;
                                 //$display("using buffer[0]\n");
                               end
                               else 
                               begin
                                 index_in <= ~index_in;
                                 buffer[1] <= din;
                                 //$display("using buffer[1]\n");
                               end                               
                               current_state_in = WAIT_REQ;                                                      
                               ackout_v <= 1;
                           end
                           else
                           begin
                               //$display("buffer is full\n");
                           end    
                       end                   
                       else
                       begin
                          add_c <= 0;     
                          ackout_v <= 0;
                          reqout_v <= 0;
                       end                      
                end                
                WAIT_REQ:
                begin
                    add_c <= 0;
                    if (ten == 1)
                     begin
                         current_state_in <= TEST;
                     end
                     else  if(req_in == 0)
                    begin
                        current_state_in <= WAIT_DATA;
                        ackout_v <= 0;
                    end                    
                end
                TEST:
                begin
                    if(ten == 0)
                    begin
                       current_state_in <=  WAIT_DATA;                   
                    end
                    else
                    begin
                        buffer[0] <= din;
                    end
                end            
            endcase
        end
    end
    
    always@(posedge clk)//state machine of output
    begin
        if(rst == 1)
        begin
            reqout_v <= 0;
            current_state_out <= PRE_SEND;
            index_out <= 0;
            reduce_c <= 0;
        end else
        begin
            case(current_state_out)
                PRE_SEND:
                begin
                    if(ten == 1)
                    begin
                        current_state_out <= TEST;
                    end
                    else if(count_b != 0)
                    begin
                        //$display("sending buffer %d\n", index_out);
                        index_out <= ~index_out;
                        reqout_v <= 1;
                        current_state_out <= WAIT_ACK;                       
                    end
                    //else $display("buffer is empty\n");                   
                end
                WAIT_ACK:
                begin
                    if(ten == 1)
                    begin
                        current_state_out <= TEST;
                    end
                    else if(ack_in == 1)
                    begin
                       reduce_c <= 1;
                       reqout_v <= 0;
                       current_state_out <= WAIT_ACK_DOWN;
                    end
                end
                WAIT_ACK_DOWN:
                begin
                    reduce_c <= 0;
                    if(ten == 1)
                    begin
                        current_state_out <= TEST;
                    end
                    else if(ack_in == 0)   current_state_out <= PRE_SEND;
                end
                TEST:
                begin
                    if(ten == 0)
                    begin
                        current_state_out <= PRE_SEND;
                    end
                    else
                    begin
                        reqout_v <= 1;
                        index_out <= 0;
                    end
                end
            endcase
        end
    end
endmodule