sk.v

来自「自己写一个关于维mesh结构的noc网络」· Verilog 代码 · 共 93 行

/*
SK (select and keep) module is used to select communicated data which dependent on the flit type
and keep the channel request to the crossbar during the whole packet.
*/
`timescale 1ns/1ps
module SK(rst, ack_in, din_3, din, dout, did, req_c);
    input rst, ack_in;
    input [33:0] din_3, din;
    output [33:0] dout;
    output [2:0] did;
    output req_c;
    reg [2:0] did_r;
    //reg head, tail;
    wire head, tail; //req;
    reg reqc_old;
    
    assign head = din[33];
    assign tail = din[32];
    
    assign dout[33:0] = (head == 1)? din_3[33:0] : din[33:0];
    assign did[2:0] = did_r[2:0];
    
    //assign req = (~rst &(head | (req & ~tail)));
    //assign reqc_old = req_c & ~ack_in;
    assign req_c =  reqc_old;//((req | reqc_old) & (~rst));
    
    always @(negedge tail or posedge head)
    begin
        if(head == 1)
        begin
            reqc_old <= 1;
        end
        else if(tail == 0)
            reqc_old <= 0;
    end
    
    always @(posedge head)//This method is only suit for this kind of packet which contains only one head flit.
    begin
        did_r[2:0] <= din[2:0];
    end
    
/*    always @(posedge rst or din[33])
    begin
        if(rst == 1)
        head <= 0;
        //tail <= 0;
        else
        head <= din[33];
    end*/
    
endmodule

module test_sk();
    reg rst, ack_in, clk;
    reg [33:0] din3, din;
    wire [33:0] dout;
    wire [2:0] did;
    wire req_c;
    
    SK test(.rst(rst), .ack_in(ack_in), .din_3(din3), .din(din), .dout(dout), .did(did), .req_c(req_c));
    
    always
    begin
        #5 clk = ~clk;        
    end
    
    initial
    begin
        clk = 1;
        rst = 1;
        ack_in = 0;
        din3 = 0;
        din = 0;
        #5;
        rst = 0;
        #5;
        din3 = 34'b1000011010101010101010100011101001;
        din = 34'b1011010101010101010100011101001010;
        #5;
        ack_in = 1;
        #5;
        ack_in = 0;
        din3 = 34'b0000000000000000000000000000000000;
        din = 34'b0100000000000000000000000000000000;
        #10;
        ack_in = 1;
        din3 = 34'b0000000000000000000000000000000000;
        din = 34'b0000000000000000000000000000000000;
        #10;
        ack_in = 0;        
    end
endmodule