crossbar.v.bak

自己写一个关于维mesh结构的noc网络

module SSC(req_c, did, req);//select signal creator
    input req_c;
    input [2:0] did;// 1 for east, 2 for south, 3 for west, 4 for north, 5 for core.
    output [4:0] req;//4th bit for east, 3rd-south, 2nd-west, 1st-north, 0-core.
    wire A, B, C, D, E;
    
    assign A = ~did[2] & ~did[1] & did[0];//001
    assign B = ~did[2] & did[1] & ~did[0];//010
    assign C = ~did[2] & did[1] & did[0];//011
    assign D = did[2] & ~did[1] & ~did[0];//100
    assign E = did[2] & ~did[1] & did[0];//101
    
    assign req[4] = A & req_c;
    assign req[3] = B & req_c;
    assign req[2] = C & req_c;
    assign req[1] = D & req_c;
    assign req[0] = E & req_c;
endmodule

module OPA(req, mask);//output port arbiter
   input [4:0] req;//4th from east,...
   output [4:0] mask;//4th for east,...
   
   assign mask[4] = req[4];
   assign mask[3] = ~req[4] & req[3];
   assign mask[2] = ~req[4] & ~req[3] & req[2];
   assign mask[1] = ~req[4] & ~req[3] & ~req[2] & req[1];
   assign mask[0] = ~req[4] & ~req[3] & ~req[2] & ~req[1] & req[0];
endmodule

module crossbar5x5(reqin_east,   din_east,   ackout_east,  reqc_east,  did_east,
                   reqin_south,  din_south,  ackout_south, reqc_south, did_south,
                   reqin_west,   din_west,   ackout_west,  reqc_west,  did_west,                   
                   reqin_north,  din_north,  ackout_north, reqc_north, did_north,
                   reqin_core,   din_core,   ackout_core,  reqc_core,  did_core,
                   reqout_east,  dout_east,  ackin_east,
                   reqout_south, dout_south, ackin_south,
                   reqout_west,  dout_west,  ackin_west,
                   reqout_north, dout_north, ackin_north,
                   reqout_core,  dout_core,  ackin_core,
                   clk, ten, rsen
                   );
    input clk, ten, rsen;
    input reqin_east, reqc_east, ackin_east;
    input [2:0] did_east;
    input [33:0] din_east;
    output ackout_east, reqout_east;
    output [33:0] dout_east;
    
    input reqin_south, reqc_south, ackin_south;
    input [2:0] did_south;
    input [33:0] din_south;
    output ackout_south, reqout_south;
    output [33:0] dout_south;
    
    input reqin_west, reqc_west, ackin_west;
    input [2:0] did_west;
    input [33:0] din_west;
    output ackout_west, reqout_west;
    output [33:0] dout_west;
    
    input reqin_north, reqc_north, ackin_north;
    input [2:0] did_north;
    input [33:0] din_north;
    output ackout_north, reqout_north;
    output [33:0] dout_north;
    
    input reqin_core, reqc_core, ackin_core;
    input [2:0] did_core;
    input [33:0] din_core;
    output ackout_core, reqout_core;
    output [33:0] dout_core;
    
    wire [4:0] east_req, south_req, west_req, north_req, core_req;//SSC output
    wire [4:0] req_east, req_south, req_west, req_north, req_core;
    wire [4:0] mask_east, mask_south, mask_west,  mask_north, mask_core;
    wire [4:0] mask_east_dft, mask_south_dft, mask_west_dft,  mask_north_dft, mask_core_dft;
    
    assign req_east[4:0] = {east_req[4], south_req[4], west_req[4], north_req[4], core_req[4]};
    assign req_south[4:0] = {east_req[3], south_req[3], west_req[3], north_req[3], core_req[3]};
    assign req_west[4:0] = {east_req[2], south_req[2], west_req[2], north_req[2], core_req[2]};
    assign req_north[4:0] = {east_req[1], south_req[1], west_req[1], north_req[1], core_req[1]};
    assign req_core[4:0] = {east_req[0], south_req[0], west_req[0], north_req[0], core_req[0]};
    
    reg [33:0] dout_east_r, dout_south_r, dout_west_r, dout_north_r, dout_core_r;
    reg reqout_east_r, reqout_south_r, reqout_west_r, reqout_north_r, reqout_core_r;
    reg ackin_east_r, ackin_south_r, ackin_west_r, ackin_north_r, ackin_core_r;
    
    SSC ssc_east(.req_c(reqc_east), .did(did_east), .req(east_req));
    SSC ssc_south(.req_c(reqc_south), .did(did_south), .req(south_req));
    SSC ssc_west(.req_c(reqc_west), .did(did_west), .req(west_req));
    SSC ssc_north(.req_c(reqc_north), .did(did_north), .req(north_req));
    SSC ssc_core(.req_c(reqc_core), .did(did_core), .req(core_req));
    
    OPA opa_east(.req(req_east), .mask(mask_east));
    OPA opa_south(.req(req_south), .mask(mask_south));
    OPA opa_west(.req(req_west), .mask(mask_west));
    OPA opa_north(.req(req_north), .mask(mask_north));
    OPA opa_core(.req(req_core), .mask(mask_core));
    
    assign mask_east_dft = (ten == 1)? ((rsen == 1)? 'b00001: 'b00100): mask_east;
    assign mask_south_dft = (ten == 1)? 'b00010 : mask_south;
    assign mask_west_dft = (ten == 1)? 'b10000 : mask_west;
    assign mask_north_dft = (ten == 1)? ((rsen == 1)? 'b00001: 'b01000): mask_north;
    assign mask_core_dft = (ten == 1)? : mask_core;
    
    assign dout_east = dout_east_r;
    assign dout_south = dout_south_r;
    assign dout_west = dout_west_r;
    assign dout_north = dout_north_r;
    assign dout_core = dout_core_r;
    
    assign reqout_east = reqout_east_r;
    assign reqout_south = reqout_south_r;
    assign reqout_west = reqout_west_r;
    assign reqout_north = reqout_north_r;
    assign reqout_core = reqout_core_r;
    
    assign ackout_east = (east_req[4] & ackin_east_r) | (east_req[3] & ackin_south_r) | (east_req[2] & ackin_west_r) |
                         (east_req[1] & ackin_north_r) | (east_req[0] & ackin_core_r);
    assign ackout_south = (south_req[4] & ackin_east_r) | (south_req[3] & ackin_south_r) | (south_req[2] & ackin_west_r) |
                         (south_req[1] & ackin_north_r) | (south_req[0] & ackin_core_r);
    assign ackout_west = (west_req[4] & ackin_east_r) | (west_req[3] & ackin_south_r) | (west_req[2] & ackin_west_r) |
                         (west_req[1] & ackin_north_r) | (west_req[0] & ackin_core_r);
    assign ackout_north = (north_req[4] & ackin_east_r) | (north_req[3] & ackin_south_r) | (north_req[2] & ackin_west_r) |
                         (north_req[1] & ackin_north_r) | (north_req[0] & ackin_core_r);
    assign ackout_core = (core_req[4] & ackin_east_r) | (core_req[3] & ackin_south_r) | (core_req[2] & ackin_west_r) |
                         (core_req[1] & ackin_north_r) | (core_req[0] & ackin_core_r);                                                  
    
    always @(posedge clk)
    begin
        ackin_east_r <= ackin_east;
        ackin_south_r <= ackin_south;
        ackin_west_r <= ackin_west;
        ackin_north_r <= ackin_north;
        ackin_core_r <= ackin_core;
        
        dout_east_r <= (mask_east_dft[4] == 1)? din_east : (mask_east_dft[3]? din_south : (mask_east_dft[2]? din_west : 
                       (mask_east_dft[1]? din_north : din_core)));
        dout_south_r <= (mask_south_dft[4] == 1)? din_east : (mask_south_dft[3]? din_south : (mask_south_dft[2]? din_west : 
                       (mask_south_dft[1]? din_north : din_core)));
        dout_west_r <= (mask_west_dft[4] == 1)? din_east : (mask_west_dft[3]? din_south : (mask_west_dft[2]? din_west : 
                       (mask_west_dft[1]? din_north : din_core)));
        dout_north_r <= (mask_north_dft[4] == 1)? din_east : (mask_north_dft[3]? din_south : (mask_north_dft[2]? din_west : 
                       (mask_north_dft[1]? din_north : din_core)));
        dout_core_r <= (mask_core_dft[4] == 1)? din_east : (mask_core_dft[3]? din_south : (mask_core_dft[2]? din_west : 
                       (mask_core_dft[1]? din_north : din_core)));
                       
                       
        reqout_east_r <= (mask_east[4] == 1)? reqin_east : (mask_east[3]? reqin_south : (mask_east[2]? reqin_west : 
                       (mask_east[1]? reqin_north : reqin_core)));
        reqout_south_r <= (mask_south[4] == 1)? reqin_east : (mask_south[3]? reqin_south : (mask_south[2]? reqin_west : 
                       (mask_south[1]? reqin_north : reqin_core)));
        reqout_west_r <= (mask_west[4] == 1)? reqin_east : (mask_west[3]? reqin_south : (mask_west[2]? reqin_west : 
                       (mask_west[1]? reqin_north : reqin_core)));
        reqout_north_r <= (mask_north[4] == 1)? reqin_east : (mask_north[3]? reqin_south : (mask_north[2]? reqin_west : 
                       (mask_north[1]? reqin_north : reqin_core)));
        reqout_core_r <= (mask_core[4] == 1)? reqin_east : (mask_core[3]? reqin_south : (mask_core[2]? reqin_west : 
                       (mask_core[1]? reqin_north : reqin_core)));
                       
    end
    
endmodule