_primary.vhd

来自「自己写一个关于维mesh结构的noc网络」· VHDL 代码 · 共 21 行

library verilog;
use verilog.vl_types.all;
entity sender is
    generic(
        IDLE            : integer := 0;
        SEND_HEAD       : integer := 1;
        SEND_TAIL       : integer := 2;
        WAIT_ACK_HEAD   : integer := 3;
        WAIT_ACK_TAIL   : integer := 4;
        WAIT_ACKH_DOWN  : integer := 5;
        WAIT_ACKT_DOWN  : integer := 6
    );
    port(
        clk             : in     vl_logic;
        send            : in     vl_logic;
        req_out         : out    vl_logic;
        dout            : out    vl_logic_vector(33 downto 0);
        ack_in          : in     vl_logic
    );
end sender;