_primary.vhd

自己写一个关于维mesh结构的noc网络

library verilog;
use verilog.vl_types.all;
entity crossbar5x5 is
    port(
        reqin_east      : in     vl_logic;
        din_east        : in     vl_logic_vector(33 downto 0);
        ackout_east     : out    vl_logic;
        reqc_east       : in     vl_logic;
        did_east        : in     vl_logic_vector(2 downto 0);
        reqin_south     : in     vl_logic;
        din_south       : in     vl_logic_vector(33 downto 0);
        ackout_south    : out    vl_logic;
        reqc_south      : in     vl_logic;
        did_south       : in     vl_logic_vector(2 downto 0);
        reqin_west      : in     vl_logic;
        din_west        : in     vl_logic_vector(33 downto 0);
        ackout_west     : out    vl_logic;
        reqc_west       : in     vl_logic;
        did_west        : in     vl_logic_vector(2 downto 0);
        reqin_north     : in     vl_logic;
        din_north       : in     vl_logic_vector(33 downto 0);
        ackout_north    : out    vl_logic;
        reqc_north      : in     vl_logic;
        did_north       : in     vl_logic_vector(2 downto 0);
        reqin_core      : in     vl_logic;
        din_core        : in     vl_logic_vector(33 downto 0);
        ackout_core     : out    vl_logic;
        reqc_core       : in     vl_logic;
        did_core        : in     vl_logic_vector(2 downto 0);
        reqout_east     : out    vl_logic;
        dout_east       : out    vl_logic_vector(33 downto 0);
        ackin_east      : in     vl_logic;
        reqout_south    : out    vl_logic;
        dout_south      : out    vl_logic_vector(33 downto 0);
        ackin_south     : in     vl_logic;
        reqout_west     : out    vl_logic;
        dout_west       : out    vl_logic_vector(33 downto 0);
        ackin_west      : in     vl_logic;
        reqout_north    : out    vl_logic;
        dout_north      : out    vl_logic_vector(33 downto 0);
        ackin_north     : in     vl_logic;
        reqout_core     : out    vl_logic;
        dout_core       : out    vl_logic_vector(33 downto 0);
        ackin_core      : in     vl_logic;
        clk             : in     vl_logic;
        ten             : in     vl_logic;
        rsen            : in     vl_logic
    );
end crossbar5x5;