main_dct.v

verilog code for dct

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    00:33:07 12/24/2008 
// Design Name: 
// Module Name:    main_dct 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module main_dct(
    input clk,
    input [15:0] data_in,
    input WE,
    input [5:0] indi_in,
    output full,
    output busy,
    output done,
    output edone,
    output reg [5:0] xk_india,
	 output  [15:0] dct_verify,
    output dv
    );


  wire [5:0]xn_index,xk_indi;
  wire rfd;
  wire [15:0]xn_re,xk_re,xk_im;
  wire [15:0] p1,p2,tempa,tempb;
  wire start;
  
  reg [15:0] xn_im=0;
  reg fwd_inv=1;
  reg fwd_inv_we=1;
  reg [15:0] steady_re [0:63];
  reg [15:0] steady_im [0:63];
  
  integer i;
  //reg [3:0] scale_sch=0;
  //reg scale_sch_we=0;
  
  initial 
  begin 
  steady_re[0] = 16'b0001000000000000;steady_im[0] = 16'b0000000000000000;
 steady_re[1] = 16'b0001011010011111;steady_im[1] = 16'b1111111101110010;
steady_re[2] = 16'b0001011010011001;steady_im[2] = 16'b1111111011100100;
steady_re[3] = 16'b0001011010010001;steady_im[3] = 16'b1111111001010110;
steady_re[4] = 16'b0001011010000100;steady_im[4] = 16'b1111110111001000;
steady_re[5] = 16'b0001011001110101;steady_im[5] = 16'b1111110100111011;
steady_re[6] = 16'b0001011001100010;steady_im[6] = 16'b1111110010101110;
steady_re[7] = 16'b0001011001001011;steady_im[7] = 16'b1111110000100010;
steady_re[8] = 16'b0001011000110001;steady_im[8] = 16'b1111101110010110;
steady_re[9] = 16'b0001011000010100;steady_im[9] = 16'b1111101100001011;
steady_re[10] = 16'b0001010111110011;steady_im[10] = 16'b1111101010000001;
steady_re[11] = 16'b0001010111001111;steady_im[11] = 16'b1111100111110111;
steady_re[12] = 16'b0001010110100111;steady_im[12] = 16'b1111100101101110;
steady_re[13] = 16'b0001010101111100;steady_im[13] = 16'b1111100011100111;
steady_re[14] = 16'b0001010101001110;steady_im[14] = 16'b1111100001100001;
steady_re[15] = 16'b0001010100011100;steady_im[15] = 16'b1111011111011011;
steady_re[16] = 16'b0001010011100111;steady_im[16] = 16'b1111011101010111;
steady_re[17] = 16'b0001010010101111;steady_im[17] = 16'b1111011011010101;
steady_re[18] = 16'b0001010001110100;steady_im[18] = 16'b1111011001010011;
steady_re[19] = 16'b0001010000110110;steady_im[19] = 16'b1111010111010100;
steady_re[20] = 16'b0001001111110100;steady_im[20] = 16'b1111010101010101;
steady_re[21] = 16'b0001001110110000;steady_im[21] = 16'b1111010011011001;
steady_re[22] = 16'b0001001101101000;steady_im[22] = 16'b1111010001011110;
steady_re[23] = 16'b0001001100011110;steady_im[23] = 16'b1111001111100101;
steady_re[24] = 16'b0001001011010000;steady_im[24] = 16'b1111001101101110;
steady_re[25] = 16'b0001001010000000;steady_im[25] = 16'b1111001011111001;
steady_re[26] = 16'b0001001000101100;steady_im[26] = 16'b1111001010000101;
steady_re[27] = 16'b0001000111010110;steady_im[27] = 16'b1111001000010100;
steady_re[28] = 16'b0001000101111110;steady_im[28] = 16'b1111000110100101;
steady_re[29] = 16'b0001000100100010;steady_im[29] = 16'b1111000100111000;
steady_re[30] = 16'b0001000011000100;steady_im[30] = 16'b1111000011001110;
steady_re[31] = 16'b0001000001100011;steady_im[31] = 16'b1111000001100110;
steady_re[32] = 16'b0001000000000000;steady_im[32] = 16'b1111000000000000;
steady_re[33] = 16'b0000111110011010;steady_im[33] = 16'b1110111110011101;
steady_re[34] = 16'b0000111100110010;steady_im[34] = 16'b1110111100111100;
steady_re[35] = 16'b0000111011000111;steady_im[35] = 16'b1110111011011110;
steady_re[36] = 16'b0000111001011011;steady_im[36] = 16'b1110111010000010;
steady_re[37] = 16'b0000110111101100;steady_im[37] = 16'b1110111000101001;
steady_re[38] = 16'b0000110101111010;steady_im[38] = 16'b1110110111010011;
steady_re[39] = 16'b0000110100000111;steady_im[39] = 16'b1110110110000000;
steady_re[40] = 16'b0000110010010010;steady_im[40] = 16'b1110110100110000;
steady_re[41] = 16'b0000110000011011;steady_im[41] = 16'b1110110011100010;
steady_re[42] = 16'b0000101110100010;steady_im[42] = 16'b1110110010011000;
steady_re[43] = 16'b0000101100100111;steady_im[43] = 16'b1110110001010000;
steady_re[44] = 16'b0000101010101010;steady_im[44] = 16'b1110110000001011;
steady_re[45] = 16'b0000101000101100;steady_im[45] = 16'b1110101111001010;
steady_re[46] = 16'b0000100110101100;steady_im[46] = 16'b1110101110001100;
steady_re[47] = 16'b0000100100101011;steady_im[47] = 16'b1110101101010000;
steady_re[48] = 16'b0000100010101000;steady_im[48] = 16'b1110101100011000;
steady_re[49] = 16'b0000100000100100;steady_im[49] = 16'b1110101011100100;
steady_re[50] = 16'b0000011110011111;steady_im[50] = 16'b1110101010110010;
steady_re[51] = 16'b0000011100011001;steady_im[51] = 16'b1110101010000100;
steady_re[52] = 16'b0000011010010001;steady_im[52] = 16'b1110101001011001;
steady_re[53] = 16'b0000011000001001;steady_im[53] = 16'b1110101000110001;
steady_re[54] = 16'b0000010101111111;steady_im[54] = 16'b1110101000001101;
steady_re[55] = 16'b0000010011110101;steady_im[55] = 16'b1110100111101100;
steady_re[56] = 16'b0000010001101010;steady_im[56] = 16'b1110100111001111;
steady_re[57] = 16'b0000001111011110;steady_im[57] = 16'b1110100110110101;
steady_re[58] = 16'b0000001101010010;steady_im[58] = 16'b1110100110011110;
steady_re[59] = 16'b0000001011000101;steady_im[59] = 16'b1110100110001011;
steady_re[60] = 16'b0000001000111000;steady_im[60] = 16'b1110100101111011;
steady_re[61] = 16'b0000000110101010;steady_im[61] = 16'b1110100101101111;
steady_re[62] = 16'b0000000100011100;steady_im[62] = 16'b1110100101100110;
steady_re[63] = 16'b0000000010001110;steady_im[63] = 16'b1110100101100001;

  end
  
  
  //assign tempa = p1>>3;
  //assign tempb = p2>>3;
  //assign addA = tempa[38:23];
  //assign addB = tempb[38:23];
  assign dct_verify = p1 + p2;  
  assign tempa = steady_re[xk_indi];
  assign tempb = steady_im[xk_indi];
  
  always@(posedge clk)
  xk_india<=xk_indi;
 
FFT u11(
  .fwd_inv_we(fwd_inv_we), .rfd(rfd), .start(start), .fwd_inv(fwd_inv), .dv(dv), .done(done), .clk(clk), .busy(busy), .edone(edone),
          .xn_re(xn_re), .xk_im(xk_im), .xn_index(xn_index), .xk_re(xk_re), .xn_im(xn_im), .xk_indi(xk_indi));
  
  

RAM_parth uut (
		.indi_in(indi_in), 
		.index_out(xn_index), 
		.clk(clk), 
		.WE(WE), 
		.rfd(rfd), 
		.full(full), 
		.data_in(data_in), 
		.data_out(xn_re), 
		.start(start)
	);
	
	MULT uut1 (
		.clk(clk), 
		.a(xk_re), 
		.b(tempa), 
		.p(p1)
	);
	
	MULT uut2 (
		.clk(clk), 
		.a(xk_im), 
		.b(tempb), 
		.p(p2)
	);





endmodule