num_count.tan.qmsg

verilog语言写的一个四层电梯程序

{ "Info" "ITDB_TSU_RESULT" "count2\[18\] Alarm clk0 10.460 ns register " "Info: tsu for register \"count2\[18\]\" (data pin = \"Alarm\", clock pin = \"clk0\") is 10.460 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.365 ns + Longest pin register " "Info: + Longest pin to register delay is 13.365 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Alarm 1 PIN PIN_3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'Alarm'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { Alarm } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.963 ns) + CELL(0.590 ns) 7.022 ns always1~30 2 COMB LC_X4_Y19_N2 4 " "Info: 2: + IC(4.963 ns) + CELL(0.590 ns) = 7.022 ns; Loc. = LC_X4_Y19_N2; Fanout = 4; COMB Node = 'always1~30'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.553 ns" { Alarm always1~30 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.390 ns) + CELL(0.442 ns) 10.854 ns count2\[22\]~1450 3 COMB LC_X21_Y12_N2 23 " "Info: 3: + IC(3.390 ns) + CELL(0.442 ns) = 10.854 ns; Loc. = LC_X21_Y12_N2; Fanout = 23; COMB Node = 'count2\[22\]~1450'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.832 ns" { always1~30 count2[22]~1450 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.644 ns) + CELL(0.867 ns) 13.365 ns count2\[18\] 4 REG LC_X20_Y11_N7 4 " "Info: 4: + IC(1.644 ns) + CELL(0.867 ns) = 13.365 ns; Loc. = LC_X20_Y11_N7; Fanout = 4; REG Node = 'count2\[18\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.511 ns" { count2[22]~1450 count2[18] } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.368 ns ( 25.20 % ) " "Info: Total cell delay = 3.368 ns ( 25.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.997 ns ( 74.80 % ) " "Info: Total interconnect delay = 9.997 ns ( 74.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "13.365 ns" { Alarm always1~30 count2[22]~1450 count2[18] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "13.365 ns" { Alarm Alarm~out0 always1~30 count2[22]~1450 count2[18] } { 0.000ns 0.000ns 4.963ns 3.390ns 1.644ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clk0\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 50; CLK Node = 'clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns count2\[18\] 2 REG LC_X20_Y11_N7 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X20_Y11_N7; Fanout = 4; REG Node = 'count2\[18\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk0 count2[18] } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk0 count2[18] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.942 ns" { clk0 clk0~out0 count2[18] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "13.365 ns" { Alarm always1~30 count2[22]~1450 count2[18] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "13.365 ns" { Alarm Alarm~out0 always1~30 count2[22]~1450 count2[18] } { 0.000ns 0.000ns 4.963ns 3.390ns 1.644ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.867ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk0 count2[18] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.942 ns" { clk0 clk0~out0 count2[18] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk0 Floor_Time Floor_Time~reg0 7.968 ns register " "Info: tco from clock \"clk0\" to destination pin \"Floor_Time\" through register \"Floor_Time~reg0\" is 7.968 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 2.942 ns + Longest register " "Info: + Longest clock path from clock \"clk0\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 50; CLK Node = 'clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns Floor_Time~reg0 2 REG LC_X22_Y12_N2 1 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X22_Y12_N2; Fanout = 1; REG Node = 'Floor_Time~reg0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk0 Floor_Time~reg0 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk0 Floor_Time~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.942 ns" { clk0 clk0~out0 Floor_Time~reg0 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 61 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.802 ns + Longest register pin " "Info: + Longest register to pin delay is 4.802 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Floor_Time~reg0 1 REG LC_X22_Y12_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y12_N2; Fanout = 1; REG Node = 'Floor_Time~reg0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { Floor_Time~reg0 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.694 ns) + CELL(2.108 ns) 4.802 ns Floor_Time 2 PIN PIN_94 0 " "Info: 2: + IC(2.694 ns) + CELL(2.108 ns) = 4.802 ns; Loc. = PIN_94; Fanout = 0; PIN Node = 'Floor_Time'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.802 ns" { Floor_Time~reg0 Floor_Time } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 43.90 % ) " "Info: Total cell delay = 2.108 ns ( 43.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.694 ns ( 56.10 % ) " "Info: Total interconnect delay = 2.694 ns ( 56.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.802 ns" { Floor_Time~reg0 Floor_Time } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "4.802 ns" { Floor_Time~reg0 Floor_Time } { 0.000ns 2.694ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk0 Floor_Time~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.942 ns" { clk0 clk0~out0 Floor_Time~reg0 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.802 ns" { Floor_Time~reg0 Floor_Time } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "4.802 ns" { Floor_Time~reg0 Floor_Time } { 0.000ns 2.694ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "time8~reg0 Reset clk0 -5.246 ns register " "Info: th for register \"time8~reg0\" (data pin = \"Reset\", clock pin = \"clk0\") is -5.246 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clk0\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 50; CLK Node = 'clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns time8~reg0 2 REG LC_X9_Y11_N8 3 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X9_Y11_N8; Fanout = 3; REG Node = 'time8~reg0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.456 ns" { clk0 time8~reg0 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk0 time8~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.925 ns" { clk0 clk0~out0 time8~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 51 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.186 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.186 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns Reset 1 PIN PIN_78 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_78; Fanout = 5; PIN Node = 'Reset'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.973 ns) + CELL(0.738 ns) 8.186 ns time8~reg0 2 REG LC_X9_Y11_N8 3 " "Info: 2: + IC(5.973 ns) + CELL(0.738 ns) = 8.186 ns; Loc. = LC_X9_Y11_N8; Fanout = 3; REG Node = 'time8~reg0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "6.711 ns" { Reset time8~reg0 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.213 ns ( 27.03 % ) " "Info: Total cell delay = 2.213 ns ( 27.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.973 ns ( 72.97 % ) " "Info: Total interconnect delay = 5.973 ns ( 72.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "8.186 ns" { Reset time8~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "8.186 ns" { Reset Reset~out0 time8~reg0 } { 0.000ns 0.000ns 5.973ns } { 0.000ns 1.475ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk0 time8~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.925 ns" { clk0 clk0~out0 time8~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "8.186 ns" { Reset time8~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "8.186 ns" { Reset Reset~out0 time8~reg0 } { 0.000ns 0.000ns 5.973ns } { 0.000ns 1.475ns 0.738ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 08 21:27:11 2007 " "Info: Processing ended: Sat Sep 08 21:27:11 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}