num_count.tan.qmsg

verilog语言写的一个四层电梯程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 08 21:27:10 2007 " "Info: Processing started: Sat Sep 08 21:27:10 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Num_Count -c Num_Count --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Num_Count -c Num_Count --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk0 " "Info: Assuming node \"clk0\" is an undefined clock" {  } { { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 2 -1 0 } } { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "clk0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk0 register count2\[18\] register count2\[9\] 174.95 MHz 5.716 ns Internal " "Info: Clock \"clk0\" has Internal fmax of 174.95 MHz between source register \"count2\[18\]\" and destination register \"count2\[9\]\" (period= 5.716 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.455 ns + Longest register register " "Info: + Longest register to register delay is 5.455 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count2\[18\] 1 REG LC_X20_Y11_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y11_N7; Fanout = 4; REG Node = 'count2\[18\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { count2[18] } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.590 ns) 1.118 ns Equal2~228 2 COMB LC_X20_Y11_N8 1 " "Info: 2: + IC(0.528 ns) + CELL(0.590 ns) = 1.118 ns; Loc. = LC_X20_Y11_N8; Fanout = 1; COMB Node = 'Equal2~228'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.118 ns" { count2[18] Equal2~228 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.120 ns) + CELL(0.590 ns) 2.828 ns Equal2~231 3 COMB LC_X22_Y11_N2 1 " "Info: 3: + IC(1.120 ns) + CELL(0.590 ns) = 2.828 ns; Loc. = LC_X22_Y11_N2; Fanout = 1; COMB Node = 'Equal2~231'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.710 ns" { Equal2~228 Equal2~231 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.124 ns Equal2~232 4 COMB LC_X22_Y11_N3 2 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 3.124 ns; Loc. = LC_X22_Y11_N3; Fanout = 2; COMB Node = 'Equal2~232'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "0.296 ns" { Equal2~231 Equal2~232 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.114 ns) 3.684 ns count2\[22\]~1452 5 COMB LC_X22_Y11_N0 23 " "Info: 5: + IC(0.446 ns) + CELL(0.114 ns) = 3.684 ns; Loc. = LC_X22_Y11_N0; Fanout = 23; COMB Node = 'count2\[22\]~1452'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "0.560 ns" { Equal2~232 count2[22]~1452 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.462 ns) + CELL(0.309 ns) 5.455 ns count2\[9\] 6 REG LC_X22_Y12_N1 4 " "Info: 6: + IC(1.462 ns) + CELL(0.309 ns) = 5.455 ns; Loc. = LC_X22_Y12_N1; Fanout = 4; REG Node = 'count2\[9\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.771 ns" { count2[22]~1452 count2[9] } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.717 ns ( 31.48 % ) " "Info: Total cell delay = 1.717 ns ( 31.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.738 ns ( 68.52 % ) " "Info: Total interconnect delay = 3.738 ns ( 68.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.455 ns" { count2[18] Equal2~228 Equal2~231 Equal2~232 count2[22]~1452 count2[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.455 ns" { count2[18] Equal2~228 Equal2~231 Equal2~232 count2[22]~1452 count2[9] } { 0.000ns 0.528ns 1.120ns 0.182ns 0.446ns 1.462ns } { 0.000ns 0.590ns 0.590ns 0.114ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.942 ns + Shortest register " "Info: + Shortest clock path from clock \"clk0\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 50; CLK Node = 'clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns count2\[9\] 2 REG LC_X22_Y12_N1 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X22_Y12_N1; Fanout = 4; REG Node = 'count2\[9\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk0 count2[9] } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk0 count2[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.942 ns" { clk0 clk0~out0 count2[9] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 2.942 ns - Longest register " "Info: - Longest clock path from clock \"clk0\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 50; CLK Node = 'clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns count2\[18\] 2 REG LC_X20_Y11_N7 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X20_Y11_N7; Fanout = 4; REG Node = 'count2\[18\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk0 count2[18] } "NODE_NAME" } } { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk0 count2[18] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.942 ns" { clk0 clk0~out0 count2[18] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk0 count2[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.942 ns" { clk0 clk0~out0 count2[9] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk0 count2[18] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.942 ns" { clk0 clk0~out0 count2[18] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.455 ns" { count2[18] Equal2~228 Equal2~231 Equal2~232 count2[22]~1452 count2[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.455 ns" { count2[18] Equal2~228 Equal2~231 Equal2~232 count2[22]~1452 count2[9] } { 0.000ns 0.528ns 1.120ns 0.182ns 0.446ns 1.462ns } { 0.000ns 0.590ns 0.590ns 0.114ns 0.114ns 0.309ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk0 count2[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.942 ns" { clk0 clk0~out0 count2[9] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk0 count2[18] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.942 ns" { clk0 clk0~out0 count2[18] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}