num_count.v

来自「verilog语言写的一个四层电梯程序」· Verilog 代码 · 共 62 行

module Num_Count(clk0,Start,time2,time8,Floor_Time,upled,downled,Lock,Alarm,overweight,Reset,close,open);
input Start,clk0,upled,downled,Lock,Alarm,overweight,Reset,close,open;
output time2,time8,Floor_Time;
reg [23:0] count1;
reg [22:0] count2;
reg time2,time8,Floor_Time;

always @(posedge clk0)
begin
if(Reset==1'b1)
count1<=0;
if(close==1'b1)
count1<=0;
else if((Start==1'b1)&&(Lock==1'b0)&&(Alarm==1'b0)&&(overweight==1'b0)&&(open==1'b0))
count1<=count1+1;
else if((Lock==1'b1)||(Alarm==1'b1)||(overweight==1'b1)||(open==1'b1))
count1<=count1;
else
count1<=0;
end

always @(posedge clk0)
begin
if(Reset==1'b1)
count2<=0;
else if(((upled==1'b1)||(downled==1'b1))&&(count2<8)&&(Lock==1'b0)&&(Alarm==1'b0)&&(overweight==1'b0)&&(open==1'b0))
count2<=count2+1;
else if((Lock==1'b1)||(Alarm==1'b1)||(overweight==1'b1)||(open==1'b1))
count2<=count2;
else
count2<=0;
end

always @(posedge clk0)
begin
if(Reset==1'b1)
time8<=1'b1;
else if(count1==8)
time2<=1'b1;
else if(close==1'b1)
time8<=1'b1;
else if(count1==32)
time8<=1'b1;
else if(time8==1'b1)
begin
time8<=1'b0;
time2<=1'b0;
end
else
time8<=1'b0;
end

always @(posedge clk0)
begin
if(count2==8)
Floor_Time<=1'b1;
else if(Floor_Time==1'b1)
Floor_Time<=1'b0;
else
Floor_Time<=1'b0;
end
endmodule