lift_comtrol_main.tan.qmsg

verilog语言写的一个四层电梯程序

{ "Info" "ITDB_TSU_RESULT" "up overweight clk0 9.808 ns register " "Info: tsu for register \"up\" (data pin = \"overweight\", clock pin = \"clk0\") is 9.808 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.673 ns + Longest pin register " "Info: + Longest pin to register delay is 12.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns overweight 1 PIN PIN_60 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_60; Fanout = 2; PIN Node = 'overweight'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { overweight } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.278 ns) + CELL(0.442 ns) 7.189 ns upled~88 2 COMB LC_X6_Y1_N2 9 " "Info: 2: + IC(5.278 ns) + CELL(0.442 ns) = 7.189 ns; Loc. = LC_X6_Y1_N2; Fanout = 9; COMB Node = 'upled~88'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.720 ns" { overweight upled~88 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.329 ns) + CELL(0.442 ns) 9.960 ns up~686 3 COMB LC_X12_Y9_N7 1 " "Info: 3: + IC(2.329 ns) + CELL(0.442 ns) = 9.960 ns; Loc. = LC_X12_Y9_N7; Fanout = 1; COMB Node = 'up~686'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.771 ns" { upled~88 up~686 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.590 ns) 10.995 ns up~687 4 COMB LC_X12_Y9_N8 1 " "Info: 4: + IC(0.445 ns) + CELL(0.590 ns) = 10.995 ns; Loc. = LC_X12_Y9_N8; Fanout = 1; COMB Node = 'up~687'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.035 ns" { up~686 up~687 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.292 ns) 11.731 ns up~690 5 COMB LC_X12_Y9_N2 1 " "Info: 5: + IC(0.444 ns) + CELL(0.292 ns) = 11.731 ns; Loc. = LC_X12_Y9_N2; Fanout = 1; COMB Node = 'up~690'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "0.736 ns" { up~687 up~690 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.464 ns) + CELL(0.478 ns) 12.673 ns up 6 REG LC_X12_Y9_N5 15 " "Info: 6: + IC(0.464 ns) + CELL(0.478 ns) = 12.673 ns; Loc. = LC_X12_Y9_N5; Fanout = 15; REG Node = 'up'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "0.942 ns" { up~690 up } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.713 ns ( 29.30 % ) " "Info: Total cell delay = 3.713 ns ( 29.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.960 ns ( 70.70 % ) " "Info: Total interconnect delay = 8.960 ns ( 70.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "12.673 ns" { overweight upled~88 up~686 up~687 up~690 up } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "12.673 ns" { overweight overweight~out0 upled~88 up~686 up~687 up~690 up } { 0.000ns 0.000ns 5.278ns 2.329ns 0.445ns 0.444ns 0.464ns } { 0.000ns 1.469ns 0.442ns 0.442ns 0.590ns 0.292ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 8 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.902 ns - Shortest register " "Info: - Shortest clock path from clock \"clk0\" to destination register is 2.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.711 ns) 2.902 ns up 2 REG LC_X12_Y9_N5 15 " "Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X12_Y9_N5; Fanout = 15; REG Node = 'up'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.433 ns" { clk0 up } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.12 % ) " "Info: Total cell delay = 2.180 ns ( 75.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.722 ns ( 24.88 % ) " "Info: Total interconnect delay = 0.722 ns ( 24.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.902 ns" { clk0 up } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.902 ns" { clk0 clk0~out0 up } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "12.673 ns" { overweight upled~88 up~686 up~687 up~690 up } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "12.673 ns" { overweight overweight~out0 upled~88 up~686 up~687 up~690 up } { 0.000ns 0.000ns 5.278ns 2.329ns 0.445ns 0.444ns 0.464ns } { 0.000ns 1.469ns 0.442ns 0.442ns 0.590ns 0.292ns 0.478ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.902 ns" { clk0 up } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.902 ns" { clk0 clk0~out0 up } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk0 num3 num3~reg0 8.388 ns register " "Info: tco from clock \"clk0\" to destination pin \"num3\" through register \"num3~reg0\" is 8.388 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clk0\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns num3~reg0 2 REG LC_X14_Y10_N9 6 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y10_N9; Fanout = 6; REG Node = 'num3~reg0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.456 ns" { clk0 num3~reg0 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk0 num3~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.925 ns" { clk0 clk0~out0 num3~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 62 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.239 ns + Longest register pin " "Info: + Longest register to pin delay is 5.239 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num3~reg0 1 REG LC_X14_Y10_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y10_N9; Fanout = 6; REG Node = 'num3~reg0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { num3~reg0 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.131 ns) + CELL(2.108 ns) 5.239 ns num3 2 PIN PIN_219 0 " "Info: 2: + IC(3.131 ns) + CELL(2.108 ns) = 5.239 ns; Loc. = PIN_219; Fanout = 0; PIN Node = 'num3'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.239 ns" { num3~reg0 num3 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 40.24 % ) " "Info: Total cell delay = 2.108 ns ( 40.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.131 ns ( 59.76 % ) " "Info: Total interconnect delay = 3.131 ns ( 59.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.239 ns" { num3~reg0 num3 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.239 ns" { num3~reg0 num3 } { 0.000ns 3.131ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk0 num3~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.925 ns" { clk0 clk0~out0 num3~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.239 ns" { num3~reg0 num3 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.239 ns" { num3~reg0 num3 } { 0.000ns 3.131ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "num3~reg0 In_num3 clk0 -0.316 ns register " "Info: th for register \"num3~reg0\" (data pin = \"In_num3\", clock pin = \"clk0\") is -0.316 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clk0\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns num3~reg0 2 REG LC_X14_Y10_N9 6 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y10_N9; Fanout = 6; REG Node = 'num3~reg0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.456 ns" { clk0 num3~reg0 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk0 num3~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.925 ns" { clk0 clk0~out0 num3~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 62 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.256 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.256 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns In_num3 1 PIN PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'In_num3'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { In_num3 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.180 ns) + CELL(0.607 ns) 3.256 ns num3~reg0 2 REG LC_X14_Y10_N9 6 " "Info: 2: + IC(1.180 ns) + CELL(0.607 ns) = 3.256 ns; Loc. = LC_X14_Y10_N9; Fanout = 6; REG Node = 'num3~reg0'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.787 ns" { In_num3 num3~reg0 } "NODE_NAME" } } { "Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns ( 63.76 % ) " "Info: Total cell delay = 2.076 ns ( 63.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.180 ns ( 36.24 % ) " "Info: Total interconnect delay = 1.180 ns ( 36.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.256 ns" { In_num3 num3~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.256 ns" { In_num3 In_num3~out0 num3~reg0 } { 0.000ns 0.000ns 1.180ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk0 num3~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "2.925 ns" { clk0 clk0~out0 num3~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.256 ns" { In_num3 num3~reg0 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.256 ns" { In_num3 In_num3~out0 num3~reg0 } { 0.000ns 0.000ns 1.180ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 09 18:17:50 2007 " "Info: Processing ended: Sun Sep 09 18:17:50 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}