lift_comtrol_main.tan.rpt

verilog语言写的一个四层电梯程序

; N/A           ; None        ; -6.180 ns ; Reset      ; num2~reg0         ; clk0     ;
; N/A           ; None        ; -6.180 ns ; Reset      ; up1~reg0          ; clk0     ;
; N/A           ; None        ; -6.211 ns ; Reset      ; led3~reg0         ; clk0     ;
; N/A           ; None        ; -6.250 ns ; Reset      ; openled~reg0      ; clk0     ;
; N/A           ; None        ; -6.482 ns ; Floor_Time ; Now_Floor[0]      ; clk0     ;
; N/A           ; None        ; -6.496 ns ; Time8      ; Start~reg0        ; clk0     ;
; N/A           ; None        ; -6.615 ns ; open       ; Now_Floor[1]      ; clk0     ;
; N/A           ; None        ; -6.655 ns ; open       ; upled~reg0        ; clk0     ;
; N/A           ; None        ; -6.660 ns ; open       ; openled~reg0      ; clk0     ;
; N/A           ; None        ; -6.661 ns ; open       ; downled~reg0      ; clk0     ;
; N/A           ; None        ; -6.676 ns ; Out_down4  ; down4~reg0        ; clk0     ;
; N/A           ; None        ; -6.767 ns ; Out_up1    ; up1~reg0          ; clk0     ;
; N/A           ; None        ; -6.811 ns ; Lock       ; Now_Floor[1]      ; clk0     ;
; N/A           ; None        ; -6.851 ns ; Lock       ; upled~reg0        ; clk0     ;
; N/A           ; None        ; -6.856 ns ; Lock       ; openled~reg0      ; clk0     ;
; N/A           ; None        ; -6.857 ns ; Lock       ; downled~reg0      ; clk0     ;
; N/A           ; None        ; -6.923 ns ; Reset      ; num4~reg0         ; clk0     ;
; N/A           ; None        ; -6.923 ns ; Reset      ; down4~reg0        ; clk0     ;
; N/A           ; None        ; -6.923 ns ; Reset      ; down              ; clk0     ;
; N/A           ; None        ; -6.939 ns ; open       ; Now_Floor[2]      ; clk0     ;
; N/A           ; None        ; -6.941 ns ; open       ; Now_Floor[0]      ; clk0     ;
; N/A           ; None        ; -7.098 ns ; Alarm      ; Now_Floor[1]      ; clk0     ;
; N/A           ; None        ; -7.135 ns ; Lock       ; Now_Floor[2]      ; clk0     ;
; N/A           ; None        ; -7.137 ns ; Lock       ; Now_Floor[0]      ; clk0     ;
; N/A           ; None        ; -7.138 ns ; Alarm      ; upled~reg0        ; clk0     ;
; N/A           ; None        ; -7.143 ns ; Alarm      ; openled~reg0      ; clk0     ;
; N/A           ; None        ; -7.144 ns ; Alarm      ; downled~reg0      ; clk0     ;
; N/A           ; None        ; -7.210 ns ; overweight ; Now_Floor[1]      ; clk0     ;
; N/A           ; None        ; -7.250 ns ; overweight ; upled~reg0        ; clk0     ;
; N/A           ; None        ; -7.255 ns ; overweight ; openled~reg0      ; clk0     ;
; N/A           ; None        ; -7.256 ns ; overweight ; downled~reg0      ; clk0     ;
; N/A           ; None        ; -7.345 ns ; open       ; Start~reg0        ; clk0     ;
; N/A           ; None        ; -7.379 ns ; Floor_Time ; Now_Floor[1]      ; clk0     ;
; N/A           ; None        ; -7.422 ns ; Alarm      ; Now_Floor[2]      ; clk0     ;
; N/A           ; None        ; -7.424 ns ; Alarm      ; Now_Floor[0]      ; clk0     ;
; N/A           ; None        ; -7.524 ns ; Reset      ; up                ; clk0     ;
; N/A           ; None        ; -7.534 ns ; overweight ; Now_Floor[2]      ; clk0     ;
; N/A           ; None        ; -7.536 ns ; overweight ; Now_Floor[0]      ; clk0     ;
; N/A           ; None        ; -7.541 ns ; Lock       ; Start~reg0        ; clk0     ;
; N/A           ; None        ; -7.828 ns ; Alarm      ; Start~reg0        ; clk0     ;
; N/A           ; None        ; -7.940 ns ; overweight ; Start~reg0        ; clk0     ;
; N/A           ; None        ; -8.234 ns ; open       ; up                ; clk0     ;
; N/A           ; None        ; -8.430 ns ; Lock       ; up                ; clk0     ;
; N/A           ; None        ; -8.444 ns ; open       ; down              ; clk0     ;
; N/A           ; None        ; -8.640 ns ; Lock       ; down              ; clk0     ;
; N/A           ; None        ; -8.717 ns ; Alarm      ; up                ; clk0     ;
; N/A           ; None        ; -8.829 ns ; overweight ; up                ; clk0     ;
; N/A           ; None        ; -8.927 ns ; Alarm      ; down              ; clk0     ;
; N/A           ; None        ; -9.039 ns ; overweight ; down              ; clk0     ;
+---------------+-------------+-----------+------------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Sep 09 18:17:50 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Lift_comtrol_main -c Lift_comtrol_main --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk0" is an undefined clock
Info: Clock "clk0" has Internal fmax of 203.96 MHz between source register "down" and destination register "down" (period= 4.903 ns)
    Info: + Longest register to register delay is 4.642 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y10_N2; Fanout = 11; REG Node = 'down'
        Info: 2: + IC(1.656 ns) + CELL(0.590 ns) = 2.246 ns; Loc. = LC_X9_Y9_N2; Fanout = 2; COMB Node = 'always10~9'
        Info: 3: + IC(1.550 ns) + CELL(0.114 ns) = 3.910 ns; Loc. = LC_X13_Y10_N5; Fanout = 1; COMB Node = 'down~1975'
        Info: 4: + IC(0.423 ns) + CELL(0.309 ns) = 4.642 ns; Loc. = LC_X13_Y10_N2; Fanout = 11; REG Node = 'down'
        Info: Total cell delay = 1.013 ns ( 21.82 % )
        Info: Total interconnect delay = 3.629 ns ( 78.18 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk0" to destination register is 2.925 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk0'
            Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y10_N2; Fanout = 11; REG Node = 'down'
            Info: Total cell delay = 2.180 ns ( 74.53 % )
            Info: Total interconnect delay = 0.745 ns ( 25.47 % )
        Info: - Longest clock path from clock "clk0" to source register is 2.925 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk0'
            Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y10_N2; Fanout = 11; REG Node = 'down'
            Info: Total cell delay = 2.180 ns ( 74.53 % )
            Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "up" (data pin = "overweight", clock pin = "clk0") is 9.808 ns
    Info: + Longest pin to register delay is 12.673 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_60; Fanout = 2; PIN Node = 'overweight'
        Info: 2: + IC(5.278 ns) + CELL(0.442 ns) = 7.189 ns; Loc. = LC_X6_Y1_N2; Fanout = 9; COMB Node = 'upled~88'
        Info: 3: + IC(2.329 ns) + CELL(0.442 ns) = 9.960 ns; Loc. = LC_X12_Y9_N7; Fanout = 1; COMB Node = 'up~686'
        Info: 4: + IC(0.445 ns) + CELL(0.590 ns) = 10.995 ns; Loc. = LC_X12_Y9_N8; Fanout = 1; COMB Node = 'up~687'
        Info: 5: + IC(0.444 ns) + CELL(0.292 ns) = 11.731 ns; Loc. = LC_X12_Y9_N2; Fanout = 1; COMB Node = 'up~690'
        Info: 6: + IC(0.464 ns) + CELL(0.478 ns) = 12.673 ns; Loc. = LC_X12_Y9_N5; Fanout = 15; REG Node = 'up'
        Info: Total cell delay = 3.713 ns ( 29.30 % )
        Info: Total interconnect delay = 8.960 ns ( 70.70 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk0" to destination register is 2.902 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk0'
        Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X12_Y9_N5; Fanout = 15; REG Node = 'up'
        Info: Total cell delay = 2.180 ns ( 75.12 % )
        Info: Total interconnect delay = 0.722 ns ( 24.88 % )
Info: tco from clock "clk0" to destination pin "num3" through register "num3~reg0" is 8.388 ns
    Info: + Longest clock path from clock "clk0" to source register is 2.925 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk0'
        Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y10_N9; Fanout = 6; REG Node = 'num3~reg0'
        Info: Total cell delay = 2.180 ns ( 74.53 % )
        Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.239 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y10_N9; Fanout = 6; REG Node = 'num3~reg0'
        Info: 2: + IC(3.131 ns) + CELL(2.108 ns) = 5.239 ns; Loc. = PIN_219; Fanout = 0; PIN Node = 'num3'
        Info: Total cell delay = 2.108 ns ( 40.24 % )
        Info: Total interconnect delay = 3.131 ns ( 59.76 % )
Info: th for register "num3~reg0" (data pin = "In_num3", clock pin = "clk0") is -0.316 ns
    Info: + Longest clock path from clock "clk0" to destination register is 2.925 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'clk0'
        Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y10_N9; Fanout = 6; REG Node = 'num3~reg0'
        Info: Total cell delay = 2.180 ns ( 74.53 % )
        Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 3.256 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'In_num3'
        Info: 2: + IC(1.180 ns) + CELL(0.607 ns) = 3.256 ns; Loc. = LC_X14_Y10_N9; Fanout = 6; REG Node = 'num3~reg0'
        Info: Total cell delay = 2.076 ns ( 63.76 % )
        Info: Total interconnect delay = 1.180 ns ( 36.24 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Sep 09 18:17:50 2007
    Info: Elapsed time: 00:00:01