📄 cout.tan.rpt
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Timing Analyzer report for cout
Sat Sep 08 16:00:49 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-------------+-------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------------+-------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.499 ns ; led1 ; dp1[2]~reg0 ; ; clk0 ; 0 ;
; Worst-case tco ; N/A ; None ; 6.831 ns ; dp1[1]~reg0 ; dp1[1] ; clk0 ; ; 0 ;
; Worst-case th ; N/A ; None ; -1.498 ns ; led4 ; dp1[3]~reg0 ; ; clk0 ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-------------+-------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk0 ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+-------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+-------------+----------+
; N/A ; None ; 4.499 ns ; led1 ; dp1[2]~reg0 ; clk0 ;
; N/A ; None ; 4.498 ns ; led1 ; dp1[3]~reg0 ; clk0 ;
; N/A ; None ; 4.497 ns ; led1 ; dp1[4]~reg0 ; clk0 ;
; N/A ; None ; 4.495 ns ; led1 ; dp1[5]~reg0 ; clk0 ;
; N/A ; None ; 4.056 ns ; led1 ; dp1[1]~reg0 ; clk0 ;
; N/A ; None ; 3.821 ns ; led2 ; dp1[4]~reg0 ; clk0 ;
; N/A ; None ; 3.820 ns ; led2 ; dp1[2]~reg0 ; clk0 ;
; N/A ; None ; 3.819 ns ; led2 ; dp1[3]~reg0 ; clk0 ;
; N/A ; None ; 3.570 ns ; led3 ; dp1[4]~reg0 ; clk0 ;
; N/A ; None ; 3.567 ns ; led3 ; dp1[2]~reg0 ; clk0 ;
; N/A ; None ; 3.566 ns ; led3 ; dp1[3]~reg0 ; clk0 ;
; N/A ; None ; 3.536 ns ; led2 ; dp1[5]~reg0 ; clk0 ;
; N/A ; None ; 1.554 ns ; led4 ; dp1[4]~reg0 ; clk0 ;
; N/A ; None ; 1.550 ns ; led4 ; dp1[3]~reg0 ; clk0 ;
+-------+--------------+------------+------+-------------+----------+
+-----------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A ; None ; 6.831 ns ; dp1[1]~reg0 ; dp1[1] ; clk0 ;
; N/A ; None ; 6.745 ns ; dp1[5]~reg0 ; dp1[5] ; clk0 ;
; N/A ; None ; 6.735 ns ; dp1[3]~reg0 ; dp1[3] ; clk0 ;
; N/A ; None ; 6.596 ns ; dp1[4]~reg0 ; dp1[7] ; clk0 ;
; N/A ; None ; 6.596 ns ; dp1[4]~reg0 ; dp1[4] ; clk0 ;
; N/A ; None ; 6.396 ns ; dp1[2]~reg0 ; dp1[2] ; clk0 ;
+-------+--------------+------------+-------------+--------+------------+
+-------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A ; None ; -1.498 ns ; led4 ; dp1[3]~reg0 ; clk0 ;
; N/A ; None ; -1.502 ns ; led4 ; dp1[4]~reg0 ; clk0 ;
; N/A ; None ; -3.484 ns ; led2 ; dp1[5]~reg0 ; clk0 ;
; N/A ; None ; -3.514 ns ; led3 ; dp1[3]~reg0 ; clk0 ;
; N/A ; None ; -3.515 ns ; led3 ; dp1[2]~reg0 ; clk0 ;
; N/A ; None ; -3.518 ns ; led3 ; dp1[4]~reg0 ; clk0 ;
; N/A ; None ; -3.767 ns ; led2 ; dp1[3]~reg0 ; clk0 ;
; N/A ; None ; -3.768 ns ; led2 ; dp1[2]~reg0 ; clk0 ;
; N/A ; None ; -3.769 ns ; led2 ; dp1[4]~reg0 ; clk0 ;
; N/A ; None ; -4.004 ns ; led1 ; dp1[1]~reg0 ; clk0 ;
; N/A ; None ; -4.443 ns ; led1 ; dp1[5]~reg0 ; clk0 ;
; N/A ; None ; -4.445 ns ; led1 ; dp1[4]~reg0 ; clk0 ;
; N/A ; None ; -4.446 ns ; led1 ; dp1[3]~reg0 ; clk0 ;
; N/A ; None ; -4.447 ns ; led1 ; dp1[2]~reg0 ; clk0 ;
+---------------+-------------+-----------+------+-------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Sep 08 16:00:49 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cout -c cout --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk0" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk0"
Info: tsu for register "dp1[2]~reg0" (data pin = "led1", clock pin = "clk0") is 4.499 ns
Info: + Longest pin to register delay is 7.365 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_53; Fanout = 5; PIN Node = 'led1'
Info: 2: + IC(5.158 ns) + CELL(0.738 ns) = 7.365 ns; Loc. = LC_X1_Y2_N5; Fanout = 1; REG Node = 'dp1[2]~reg0'
Info: Total cell delay = 2.207 ns ( 29.97 % )
Info: Total interconnect delay = 5.158 ns ( 70.03 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "clk0" to destination register is 2.903 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk0'
Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y2_N5; Fanout = 1; REG Node = 'dp1[2]~reg0'
Info: Total cell delay = 2.180 ns ( 75.09 % )
Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: tco from clock "clk0" to destination pin "dp1[1]" through register "dp1[1]~reg0" is 6.831 ns
Info: + Longest clock path from clock "clk0" to source register is 2.903 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk0'
Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y2_N8; Fanout = 1; REG Node = 'dp1[1]~reg0'
Info: Total cell delay = 2.180 ns ( 75.09 % )
Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 3.704 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N8; Fanout = 1; REG Node = 'dp1[1]~reg0'
Info: 2: + IC(1.580 ns) + CELL(2.124 ns) = 3.704 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'dp1[1]'
Info: Total cell delay = 2.124 ns ( 57.34 % )
Info: Total interconnect delay = 1.580 ns ( 42.66 % )
Info: th for register "dp1[3]~reg0" (data pin = "led4", clock pin = "clk0") is -1.498 ns
Info: + Longest clock path from clock "clk0" to destination register is 2.903 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk0'
Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y2_N6; Fanout = 1; REG Node = 'dp1[3]~reg0'
Info: Total cell delay = 2.180 ns ( 75.09 % )
Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 4.416 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 2; PIN Node = 'led4'
Info: 2: + IC(2.469 ns) + CELL(0.478 ns) = 4.416 ns; Loc. = LC_X1_Y2_N6; Fanout = 1; REG Node = 'dp1[3]~reg0'
Info: Total cell delay = 1.947 ns ( 44.09 % )
Info: Total interconnect delay = 2.469 ns ( 55.91 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Sat Sep 08 16:00:49 2007
Info: Elapsed time: 00:00:01
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