cout.tan.qmsg

verilog语言写的一个四层电梯程序

{ "Info" "ITDB_TSU_RESULT" "dp1\[2\]~reg0 led1 clk0 4.499 ns register " "Info: tsu for register \"dp1\[2\]~reg0\" (data pin = \"led1\", clock pin = \"clk0\") is 4.499 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.365 ns + Longest pin register " "Info: + Longest pin to register delay is 7.365 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns led1 1 PIN PIN_53 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_53; Fanout = 5; PIN Node = 'led1'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "" { led1 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.158 ns) + CELL(0.738 ns) 7.365 ns dp1\[2\]~reg0 2 REG LC_X1_Y2_N5 1 " "Info: 2: + IC(5.158 ns) + CELL(0.738 ns) = 7.365 ns; Loc. = LC_X1_Y2_N5; Fanout = 1; REG Node = 'dp1\[2\]~reg0'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "5.896 ns" { led1 dp1[2]~reg0 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns 29.97 % " "Info: Total cell delay = 2.207 ns ( 29.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.158 ns 70.03 % " "Info: Total interconnect delay = 5.158 ns ( 70.03 % )" {  } {  } 0}  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "7.365 ns" { led1 dp1[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.365 ns" { led1 led1~out0 dp1[2]~reg0 } { 0.000ns 0.000ns 5.158ns } { 0.000ns 1.469ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 47 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.903 ns - Shortest register " "Info: - Shortest clock path from clock \"clk0\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk0'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "" { clk0 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns dp1\[2\]~reg0 2 REG LC_X1_Y2_N5 1 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y2_N5; Fanout = 1; REG Node = 'dp1\[2\]~reg0'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "1.434 ns" { clk0 dp1[2]~reg0 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "2.903 ns" { clk0 dp1[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk0 clk0~out0 dp1[2]~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "7.365 ns" { led1 dp1[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.365 ns" { led1 led1~out0 dp1[2]~reg0 } { 0.000ns 0.000ns 5.158ns } { 0.000ns 1.469ns 0.738ns } } } { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "2.903 ns" { clk0 dp1[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk0 clk0~out0 dp1[2]~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk0 dp1\[1\] dp1\[1\]~reg0 6.831 ns register " "Info: tco from clock \"clk0\" to destination pin \"dp1\[1\]\" through register \"dp1\[1\]~reg0\" is 6.831 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 2.903 ns + Longest register " "Info: + Longest clock path from clock \"clk0\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk0'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "" { clk0 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns dp1\[1\]~reg0 2 REG LC_X1_Y2_N8 1 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y2_N8; Fanout = 1; REG Node = 'dp1\[1\]~reg0'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "1.434 ns" { clk0 dp1[1]~reg0 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "2.903 ns" { clk0 dp1[1]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk0 clk0~out0 dp1[1]~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 47 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.704 ns + Longest register pin " "Info: + Longest register to pin delay is 3.704 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dp1\[1\]~reg0 1 REG LC_X1_Y2_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N8; Fanout = 1; REG Node = 'dp1\[1\]~reg0'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "" { dp1[1]~reg0 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.580 ns) + CELL(2.124 ns) 3.704 ns dp1\[1\] 2 PIN PIN_54 0 " "Info: 2: + IC(1.580 ns) + CELL(2.124 ns) = 3.704 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'dp1\[1\]'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "3.704 ns" { dp1[1]~reg0 dp1[1] } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 57.34 % " "Info: Total cell delay = 2.124 ns ( 57.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.580 ns 42.66 % " "Info: Total interconnect delay = 1.580 ns ( 42.66 % )" {  } {  } 0}  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "3.704 ns" { dp1[1]~reg0 dp1[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.704 ns" { dp1[1]~reg0 dp1[1] } { 0.000ns 1.580ns } { 0.000ns 2.124ns } } }  } 0}  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "2.903 ns" { clk0 dp1[1]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk0 clk0~out0 dp1[1]~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "3.704 ns" { dp1[1]~reg0 dp1[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "3.704 ns" { dp1[1]~reg0 dp1[1] } { 0.000ns 1.580ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "dp1\[3\]~reg0 led4 clk0 -1.498 ns register " "Info: th for register \"dp1\[3\]~reg0\" (data pin = \"led4\", clock pin = \"clk0\") is -1.498 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.903 ns + Longest register " "Info: + Longest clock path from clock \"clk0\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk0'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "" { clk0 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns dp1\[3\]~reg0 2 REG LC_X1_Y2_N6 1 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y2_N6; Fanout = 1; REG Node = 'dp1\[3\]~reg0'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "1.434 ns" { clk0 dp1[3]~reg0 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "2.903 ns" { clk0 dp1[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk0 clk0~out0 dp1[3]~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 47 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.416 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns led4 1 PIN PIN_28 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 2; PIN Node = 'led4'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "" { led4 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.469 ns) + CELL(0.478 ns) 4.416 ns dp1\[3\]~reg0 2 REG LC_X1_Y2_N6 1 " "Info: 2: + IC(2.469 ns) + CELL(0.478 ns) = 4.416 ns; Loc. = LC_X1_Y2_N6; Fanout = 1; REG Node = 'dp1\[3\]~reg0'" {  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "2.947 ns" { led4 dp1[3]~reg0 } "NODE_NAME" } "" } } { "cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns 44.09 % " "Info: Total cell delay = 1.947 ns ( 44.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.469 ns 55.91 % " "Info: Total interconnect delay = 2.469 ns ( 55.91 % )" {  } {  } 0}  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "4.416 ns" { led4 dp1[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.416 ns" { led4 led4~out0 dp1[3]~reg0 } { 0.000ns 0.000ns 2.469ns } { 0.000ns 1.469ns 0.478ns } } }  } 0}  } { { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "2.903 ns" { clk0 dp1[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk0 clk0~out0 dp1[3]~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/自动电梯/显示模块/db/cout_cmp.qrpt" "" { Report "E:/自动电梯/显示模块/db/cout_cmp.qrpt" Compiler "cout" "UNKNOWN" "V1" "E:/自动电梯/显示模块/db/cout.quartus_db" { Floorplan "E:/自动电梯/显示模块/" "" "4.416 ns" { led4 dp1[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.416 ns" { led4 led4~out0 dp1[3]~reg0 } { 0.000ns 0.000ns 2.469ns } { 0.000ns 1.469ns 0.478ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 08 16:00:49 2007 " "Info: Processing ended: Sat Sep 08 16:00:49 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}