top.map.qmsg

verilog语言写的一个四层电梯程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 09 18:51:52 2007 " "Info: Processing started: Sun Sep 09 18:51:52 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITH_RANGE" "dp1 cout.v(8) " "Warning (10227): Verilog HDL Multiple Declaration warning at cout.v(8): net, port, or variable \"dp1\" was previously declared with a range" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 8 0 0 } }  } 0 10227 "Verilog HDL Multiple Declaration warning at %2!s!: net, port, or variable \"%1!s!\" was previously declared with a range" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "dp1 cout.v(4) " "Info (10151): Verilog HDL Declaration information at cout.v(4): \"dp1\" is declared here" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 4 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITH_RANGE" "dp2 cout.v(8) " "Warning (10227): Verilog HDL Multiple Declaration warning at cout.v(8): net, port, or variable \"dp2\" was previously declared with a range" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 8 0 0 } }  } 0 10227 "Verilog HDL Multiple Declaration warning at %2!s!: net, port, or variable \"%1!s!\" was previously declared with a range" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "dp2 cout.v(5) " "Info (10151): Verilog HDL Declaration information at cout.v(5): \"dp2\" is declared here" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 5 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITH_RANGE" "dp3 cout.v(8) " "Warning (10227): Verilog HDL Multiple Declaration warning at cout.v(8): net, port, or variable \"dp3\" was previously declared with a range" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 8 0 0 } }  } 0 10227 "Verilog HDL Multiple Declaration warning at %2!s!: net, port, or variable \"%1!s!\" was previously declared with a range" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "dp3 cout.v(6) " "Info (10151): Verilog HDL Declaration information at cout.v(6): \"dp3\" is declared here" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 6 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITH_RANGE" "dp4 cout.v(8) " "Warning (10227): Verilog HDL Multiple Declaration warning at cout.v(8): net, port, or variable \"dp4\" was previously declared with a range" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 8 0 0 } }  } 0 10227 "Verilog HDL Multiple Declaration warning at %2!s!: net, port, or variable \"%1!s!\" was previously declared with a range" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "dp4 cout.v(7) " "Info (10151): Verilog HDL Declaration information at cout.v(7): \"dp4\" is declared here" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 7 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../显示模块/cout.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../显示模块/cout.v" { { "Info" "ISGN_ENTITY_NAME" "1 cout " "Info: Found entity 1: cout" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../状态机/Lift_comtrol_main.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../状态机/Lift_comtrol_main.v" { { "Info" "ISGN_ENTITY_NAME" "1 Lift_comtrol_main " "Info: Found entity 1: Lift_comtrol_main" {  } { { "../状态机/Lift_comtrol_main.v" "" { Text "E:/自动电梯/状态机/Lift_comtrol_main.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../计数器/Num_Count.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../计数器/Num_Count.v" { { "Info" "ISGN_ENTITY_NAME" "1 Num_Count " "Info: Found entity 1: Num_Count" {  } { { "../计数器/Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.bdf" "" { Schematic "E:/自动电梯/顶图/top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file top1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 top1 " "Info: Found entity 1: top1" {  } { { "top1.bdf" "" { Schematic "E:/自动电梯/顶图/top1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Info: Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Lift_comtrol_main Lift_comtrol_main:inst " "Info: Elaborating entity \"Lift_comtrol_main\" for hierarchy \"Lift_comtrol_main:inst\"" {  } { { "top.bdf" "inst" { Schematic "E:/自动电梯/顶图/top.bdf" { { 16 16 192 368 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Num_Count Num_Count:inst1 " "Info: Elaborating entity \"Num_Count\" for hierarchy \"Num_Count:inst1\"" {  } { { "top.bdf" "inst1" { Schematic "E:/自动电梯/顶图/top.bdf" { { 80 560 720 304 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 Num_Count.v(15) " "Warning (10230): Verilog HDL assignment warning at Num_Count.v(15): truncated value with size 32 to match size of target (24)" {  } { { "../计数器/Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Num_Count.v(27) " "Warning (10230): Verilog HDL assignment warning at Num_Count.v(27): truncated value with size 32 to match size of target (23)" {  } { { "../计数器/Num_Count.v" "" { Text "E:/自动电梯/计数器/Num_Count.v" 27 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cout cout:inst2 " "Info: Elaborating entity \"cout\" for hierarchy \"cout:inst2\"" {  } { { "top.bdf" "inst2" { Schematic "E:/自动电梯/顶图/top.bdf" { { -128 560 680 0 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 cout.v(14) " "Warning (10230): Verilog HDL assignment warning at cout.v(14): truncated value with size 8 to match size of target (1)" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 14 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 cout.v(15) " "Warning (10230): Verilog HDL assignment warning at cout.v(15): truncated value with size 8 to match size of target (1)" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 cout.v(16) " "Warning (10230): Verilog HDL assignment warning at cout.v(16): truncated value with size 8 to match size of target (1)" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 cout.v(17) " "Warning (10230): Verilog HDL assignment warning at cout.v(17): truncated value with size 8 to match size of target (1)" {  } { { "../显示模块/cout.v" "" { Text "E:/自动电梯/显示模块/cout.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}