top.tan.summary

来自「verilog语言写的一个四层电梯程序」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.338 ns
From           : Alarm
To             : Lift_comtrol_main:inst|down
From Clock     : --
To Clock       : clk0
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.069 ns
From           : Lift_comtrol_main:inst|num1
To             : num1
From Clock     : clk0
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.762 ns
From           : In_num2
To             : Lift_comtrol_main:inst|num2
From Clock     : --
To Clock       : clk0
Failed Paths   : 0

Type           : Clock Setup: 'clk0'
Slack          : N/A
Required Time  : None
Actual Time    : 175.69 MHz ( period = 5.692 ns )
From           : Lift_comtrol_main:inst|down2
To             : Lift_comtrol_main:inst|up
From Clock     : clk0
To Clock       : clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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