top.map.rpt

verilog语言写的一个四层电梯程序

;     -- arithmetic mode                      ; 45    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 39    ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 70    ;
; Total logic cells in carry chains           ; 47    ;
; I/O pins                                    ; 31    ;
; Maximum fan-out node                        ; clk0  ;
; Maximum fan-out                             ; 70    ;
; Total fan-out                               ; 731   ;
; Average fan-out                             ; 3.43  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                    ;
+-----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+
; Compilation Hierarchy Node  ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name         ;
+-----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+
; |top                        ; 182 (0)     ; 70           ; 0           ; 0    ; 31   ; 0            ; 112 (0)      ; 1 (0)             ; 69 (0)           ; 47 (0)          ; 0 (0)      ; |top                        ;
;    |Lift_comtrol_main:inst| ; 86 (86)     ; 20           ; 0           ; 0    ; 0    ; 0            ; 66 (66)      ; 1 (1)             ; 19 (19)          ; 0 (0)           ; 0 (0)      ; |top|Lift_comtrol_main:inst ;
;    |Num_Count:inst1|        ; 96 (96)     ; 50           ; 0           ; 0    ; 0    ; 0            ; 46 (46)      ; 0 (0)             ; 50 (50)          ; 47 (47)         ; 0 (0)      ; |top|Num_Count:inst1        ;
+-----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 70    ;
; Number of registers using Synchronous Clear  ; 38    ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 49    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; 4:1                ; 24 bits   ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; Yes        ; |top|Num_Count:inst1|count1[14] ;
; 4:1                ; 23 bits   ; 46 LEs        ; 23 LEs               ; 23 LEs                 ; Yes        ; |top|Num_Count:inst1|count2[4]  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Sep 09 18:51:52 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Warning (10227): Verilog HDL Multiple Declaration warning at cout.v(8): net, port, or variable "dp1" was previously declared with a range
Info (10151): Verilog HDL Declaration information at cout.v(4): "dp1" is declared here
Warning (10227): Verilog HDL Multiple Declaration warning at cout.v(8): net, port, or variable "dp2" was previously declared with a range
Info (10151): Verilog HDL Declaration information at cout.v(5): "dp2" is declared here
Warning (10227): Verilog HDL Multiple Declaration warning at cout.v(8): net, port, or variable "dp3" was previously declared with a range
Info (10151): Verilog HDL Declaration information at cout.v(6): "dp3" is declared here
Warning (10227): Verilog HDL Multiple Declaration warning at cout.v(8): net, port, or variable "dp4" was previously declared with a range
Info (10151): Verilog HDL Declaration information at cout.v(7): "dp4" is declared here
Info: Found 1 design units, including 1 entities, in source file ../显示模块/cout.v
    Info: Found entity 1: cout
Info: Found 1 design units, including 1 entities, in source file ../状态机/Lift_comtrol_main.v
    Info: Found entity 1: Lift_comtrol_main
Info: Found 1 design units, including 1 entities, in source file ../计数器/Num_Count.v
    Info: Found entity 1: Num_Count
Info: Found 1 design units, including 1 entities, in source file top.bdf
    Info: Found entity 1: top
Info: Found 1 design units, including 1 entities, in source file top1.bdf
    Info: Found entity 1: top1
Info: Elaborating entity "top" for the top level hierarchy
Info: Elaborating entity "Lift_comtrol_main" for hierarchy "Lift_comtrol_main:inst"
Info: Elaborating entity "Num_Count" for hierarchy "Num_Count:inst1"
Warning (10230): Verilog HDL assignment warning at Num_Count.v(15): truncated value with size 32 to match size of target (24)
Warning (10230): Verilog HDL assignment warning at Num_Count.v(27): truncated value with size 32 to match size of target (23)
Info: Elaborating entity "cout" for hierarchy "cout:inst2"
Warning (10230): Verilog HDL assignment warning at cout.v(14): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(15): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(16): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(17): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(21): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(22): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(23): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(24): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(28): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(29): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(30): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(31): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(35): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(36): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(37): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(38): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(42): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(43): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(44): truncated value with size 8 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at cout.v(45): truncated value with size 8 to match size of target (1)
Warning: Port "dp1[0]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp1[1]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp1[2]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp1[3]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp1[4]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp1[5]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp1[6]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp1[7]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp2[0]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp2[1]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp2[2]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp2[3]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp2[4]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp2[5]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp2[6]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp2[7]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp3[0]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp3[1]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp3[2]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp3[3]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp3[4]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp3[5]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp3[6]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp3[7]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp4[0]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp4[1]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp4[2]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp4[3]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp4[4]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp4[5]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp4[6]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Warning: Port "dp4[7]" does not exist in entity definition of "cout".  The port's range differs between the entity definition and its actual instantiation, "cout:inst2".
Info: Implemented 213 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 14 output pins
    Info: Implemented 182 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 58 warnings
    Info: Processing ended: Sun Sep 09 18:51:59 2007
    Info: Elapsed time: 00:00:08