time_dif.v

verilog 经典例子的源码 非常适用于初学verilog的朋友们

`timescale 10ns/1ns
module time_dif;
reg ts;
parameter delay=2.6;
initial
  	begin
    	#delay  ts=1;
    	#delay  ts=0;
    	#delay  ts=1;
	#delay  ts=0;
  	end
initial  $monitor($time,,,"ts=%b",ts);
endmodule