mux21_2.v

verilog 经典例子的源码 非常适用于初学verilog的朋友们

module MUX21_2(out,a,b,sel);
input a,b,sel;
output out;
reg out;
always@(a or b or sel)
  begin
     if(sel==0) out=a;
     else       out=b;
  end
endmodule