wave1.v

verilog 经典例子的源码 非常适用于初学verilog的朋友们

`timescale 10ns/1ns
module wave1;
reg wave;
parameter cycle=10;
initial
  begin
            wave=0;
#(cycle/2)  wave=1;
#(cycle/2)  wave=0;
#(cycle/2)  wave=1;
#(cycle/2)  wave=0;
#(cycle/2)  wave=1;
#(cycle/2)  $finish ;
end
initial $monitor($time,,,"wave=%b",wave);
endmodule