cnt4.tan.qmsg

这是用VHDL设计的十进制计数器

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "cnt4.vhd" "" { Text "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/cnt4.vhd" 2 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:Q_rtl_0\|dffs\[0\] register lpm_counter:Q_rtl_0\|dffs\[3\] 175.44 MHz 5.7 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 175.44 MHz between source register \"lpm_counter:Q_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:Q_rtl_0\|dffs\[3\]\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Q_rtl_0\|dffs\[0\] 1 REG LC1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'lpm_counter:Q_rtl_0\|dffs\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "" { lpm_counter:Q_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns lpm_counter:Q_rtl_0\|dffs\[3\] 2 REG LC5 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:Q_rtl_0\|dffs\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "3.600 ns" { lpm_counter:Q_rtl_0|dffs[0] lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns ( 72.22 % ) " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 27.78 % ) " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "3.600 ns" { lpm_counter:Q_rtl_0|dffs[0] lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.600 ns" { lpm_counter:Q_rtl_0|dffs[0] lpm_counter:Q_rtl_0|dffs[3] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "" { CLK } "NODE_NAME" } "" } } { "cnt4.vhd" "" { Text "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/cnt4.vhd" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:Q_rtl_0\|dffs\[3\] 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:Q_rtl_0\|dffs\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "0.100 ns" { CLK lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 100.00 % ) " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "1.300 ns" { CLK lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "" { CLK } "NODE_NAME" } "" } } { "cnt4.vhd" "" { Text "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/cnt4.vhd" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:Q_rtl_0\|dffs\[0\] 2 REG LC1 5 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 5; REG Node = 'lpm_counter:Q_rtl_0\|dffs\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "0.100 ns" { CLK lpm_counter:Q_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 100.00 % ) " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "1.300 ns" { CLK lpm_counter:Q_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "1.300 ns" { CLK lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "1.300 ns" { CLK lpm_counter:Q_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "3.600 ns" { lpm_counter:Q_rtl_0|dffs[0] lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.600 ns" { lpm_counter:Q_rtl_0|dffs[0] lpm_counter:Q_rtl_0|dffs[3] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "1.300 ns" { CLK lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "1.300 ns" { CLK lpm_counter:Q_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[3\] lpm_counter:Q_rtl_0\|dffs\[3\] 2.800 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[3\]\" through register \"lpm_counter:Q_rtl_0\|dffs\[3\]\" is 2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "" { CLK } "NODE_NAME" } "" } } { "cnt4.vhd" "" { Text "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/cnt4.vhd" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:Q_rtl_0\|dffs\[3\] 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:Q_rtl_0\|dffs\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "0.100 ns" { CLK lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 100.00 % ) " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "1.300 ns" { CLK lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Q_rtl_0\|dffs\[3\] 1 REG LC5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:Q_rtl_0\|dffs\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "" { lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Q\[3\] 2 PIN PIN_8 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'Q\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "0.200 ns" { lpm_counter:Q_rtl_0|dffs[3] Q[3] } "NODE_NAME" } "" } } { "cnt4.vhd" "" { Text "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/cnt4.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns ( 100.00 % ) " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "0.200 ns" { lpm_counter:Q_rtl_0|dffs[3] Q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:Q_rtl_0|dffs[3] Q[3] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "1.300 ns" { CLK lpm_counter:Q_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt4" "UNKNOWN" "V1" "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/db/cnt4.quartus_db" { Floorplan "E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/" "" "0.200 ns" { lpm_counter:Q_rtl_0|dffs[3] Q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:Q_rtl_0|dffs[3] Q[3] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 21 17:40:49 2008 " "Info: Processing ended: Fri Mar 21 17:40:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}