cnt42.fit.eqn

这是用VHDL设计的十进制计数器

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--B1_dffs[0] is lpm_counter:Q1_rtl_0|dffs[0] at LC1
B1_dffs[0]_reg_input = VCC;
B1_dffs[0] = TFFE(B1_dffs[0]_reg_input, GLOBAL(CLK), , , );


--B1_dffs[1] is lpm_counter:Q1_rtl_0|dffs[1] at LC2
B1_dffs[1]_or_out = B1_dffs[0];
B1_dffs[1]_reg_input = B1_dffs[1]_or_out;
B1_dffs[1] = TFFE(B1_dffs[1]_reg_input, GLOBAL(CLK), , , );


--B1_dffs[2] is lpm_counter:Q1_rtl_0|dffs[2] at LC3
B1_dffs[2]_p1_out = B1_dffs[0] & B1_dffs[1];
B1_dffs[2]_or_out = B1_dffs[2]_p1_out;
B1_dffs[2]_reg_input = B1_dffs[2]_or_out;
B1_dffs[2] = TFFE(B1_dffs[2]_reg_input, GLOBAL(CLK), , , );


--B1_dffs[3] is lpm_counter:Q1_rtl_0|dffs[3] at LC5
B1_dffs[3]_p1_out = B1_dffs[2] & B1_dffs[0] & B1_dffs[1];
B1_dffs[3]_or_out = B1_dffs[3]_p1_out;
B1_dffs[3]_reg_input = B1_dffs[3]_or_out;
B1_dffs[3] = TFFE(B1_dffs[3]_reg_input, GLOBAL(CLK), , , );


--CLK is CLK at PIN_43
--operation mode is input

CLK = INPUT();


--Q[0] is Q[0] at PIN_4
--operation mode is output

Q[0] = OUTPUT(B1_dffs[0]);


--Q[1] is Q[1] at PIN_5
--operation mode is output

Q[1] = OUTPUT(B1_dffs[1]);


--Q[2] is Q[2] at PIN_6
--operation mode is output

Q[2] = OUTPUT(B1_dffs[2]);


--Q[3] is Q[3] at PIN_8
--operation mode is output

Q[3] = OUTPUT(B1_dffs[3]);